[llvm] [GlobalISel] Implement G_UADDO/G_UADDE/G_SADDO/G_SADDE for computeKnownBits (PR #165497)
Yatao Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 22 15:43:22 PST 2025
https://github.com/ningxinr updated https://github.com/llvm/llvm-project/pull/165497
>From 5a117b2af4b69f19e7b2c860877657e2f85a2380 Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Wed, 22 Oct 2025 14:21:01 -0700
Subject: [PATCH 1/7] [GlobalISel] Implement G_UADDO/G_UADDE/G_SADDO/G_SADDE
for computeKnownBits
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 32 +++++++++-
.../AArch64/GlobalISel/knownbits-sadde.mir | 63 +++++++++++++++++++
.../AArch64/GlobalISel/knownbits-saddo.mir | 29 +++++++++
.../AArch64/GlobalISel/knownbits-uadde.mir | 63 +++++++++++++++++++
.../AArch64/GlobalISel/knownbits-uaddo.mir | 29 +++++++++
.../legalize-trailing-zeros-undef.mir | 6 +-
.../GlobalISel/legalize-trailing-zeros.mir | 6 +-
7 files changed, 217 insertions(+), 11 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index d6f23b62519fe..2a844ee0f9fcf 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -615,7 +615,37 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
case TargetOpcode::G_UADDO:
case TargetOpcode::G_UADDE:
case TargetOpcode::G_SADDO:
- case TargetOpcode::G_SADDE:
+ case TargetOpcode::G_SADDE: {
+ if (MI.getOperand(1).getReg() == R) {
+ // If we know the result of a compare has the top bits zero, use this
+ // info.
+ if (TL.getBooleanContents(DstTy.isVector(), false) ==
+ TargetLowering::ZeroOrOneBooleanContent &&
+ BitWidth > 1)
+ Known.Zero.setBitsFrom(1);
+ break;
+ }
+
+ assert(MI.getOperand(0).getReg() == R &&
+ "We only compute knownbits for the sum here.");
+ // With UADDO_CARRY, a carry bit may be added in.
+ KnownBits Carry(1);
+ if (Opcode == TargetOpcode::G_UADDE || Opcode == TargetOpcode::G_SADDE) {
+ computeKnownBitsImpl(MI.getOperand(4).getReg(), Known, DemandedElts,
+ Depth + 1);
+ // Carry has bit width 1
+ Carry = Carry.trunc(1);
+ } else {
+ Carry.setAllZero();
+ }
+
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(3).getReg(), Known2, DemandedElts,
+ Depth + 1);
+ Known = KnownBits::computeForAddCarry(Known, Known2, Carry);
+ break;
+ }
case TargetOpcode::G_USUBO:
case TargetOpcode::G_USUBE:
case TargetOpcode::G_SSUBO:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
new file mode 100644
index 0000000000000..be1777cae827b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryInZeroOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name: CstCarryInZeroOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:01111111 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:100000?? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 127
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:01111111 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:100000?? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 127
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
new file mode 100644
index 0000000000000..40c7e25ab943a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:00011010 SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s8), %3:_(s1) = G_SADDO %0, %1
+...
+---
+name: CstCarryOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:01111110 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:10000000 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 126
+ %2:_(s8), %3:_(s1) = G_SADDO %0, %1
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
new file mode 100644
index 0000000000000..6f2aa10a1115a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryInZeroOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
+---
+name: CstCarryInZeroOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:000000?? SignBits:6
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 255
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:000000?? SignBits:6
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 255
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
new file mode 100644
index 0000000000000..b10ea6c2926b3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:00011010 SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s8), %4:_(s1) = G_UADDO %0, %1
+...
+---
+name: CstCarryOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:11111110 SignBits:7
+ ; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 254
+ %2:_(s8), %4:_(s1) = G_UADDO %0, %1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
index 57e729fb03ab6..8255e01d71864 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
@@ -40,11 +40,7 @@ body: |
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
- ; X86-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; X86-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C4]]
- ; X86-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C5]]
- ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND1]](s32), [[AND2]](s32)
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: RET 0, implicit [[MV]](s64)
%0(s64) = COPY $rdx
%1:_(s35) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
index f5d847776ec06..a429e89e8f255 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
@@ -40,11 +40,7 @@ body: |
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
- ; X86-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; X86-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C4]]
- ; X86-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C5]]
- ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND1]](s32), [[AND2]](s32)
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: RET 0, implicit [[MV]](s64)
%0(s64) = COPY $rdx
%1:_(s35) = G_TRUNC %0(s64)
>From 9c85f7f2466c94be1cf398cd213d029fce1c96f2 Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Tue, 28 Oct 2025 19:10:53 -0700
Subject: [PATCH 2/7] Fix comments
---
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 2a844ee0f9fcf..3b96d853859c8 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -628,7 +628,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
assert(MI.getOperand(0).getReg() == R &&
"We only compute knownbits for the sum here.");
- // With UADDO_CARRY, a carry bit may be added in.
+ // With [US]ADDE, a carry bit may be added in.
KnownBits Carry(1);
if (Opcode == TargetOpcode::G_UADDE || Opcode == TargetOpcode::G_SADDE) {
computeKnownBitsImpl(MI.getOperand(4).getReg(), Known, DemandedElts,
>From 8e787c259dce6dd02f69a892492e70e858a4d96e Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Thu, 30 Oct 2025 09:29:21 -0700
Subject: [PATCH 3/7] Addressed feedback
---
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir | 8 ++++----
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir | 8 ++++----
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 3b96d853859c8..1a99fad02293c 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -631,7 +631,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
// With [US]ADDE, a carry bit may be added in.
KnownBits Carry(1);
if (Opcode == TargetOpcode::G_UADDE || Opcode == TargetOpcode::G_SADDE) {
- computeKnownBitsImpl(MI.getOperand(4).getReg(), Known, DemandedElts,
+ computeKnownBitsImpl(MI.getOperand(4).getReg(), Carry, DemandedElts,
Depth + 1);
// Carry has bit width 1
Carry = Carry.trunc(1);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
index be1777cae827b..8ba600b8a5ce1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
@@ -9,7 +9,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:00011010 SignBits:3
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 24
@@ -24,7 +24,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:00011011 SignBits:3
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 24
@@ -39,7 +39,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:01111111 SignBits:1
; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:100000?? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:10000001 SignBits:1
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 127
@@ -54,7 +54,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:01111111 SignBits:1
; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:100000?? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:10000010 SignBits:1
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 127
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
index 6f2aa10a1115a..1389816e507f7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
@@ -9,7 +9,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:00011010 SignBits:3
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 24
@@ -24,7 +24,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:00011011 SignBits:3
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 24
@@ -39,7 +39,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:000000?? SignBits:6
+ ; CHECK-NEXT: %3:_ KnownBits:00000001 SignBits:7
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 255
@@ -54,7 +54,7 @@ body: |
; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
- ; CHECK-NEXT: %3:_ KnownBits:000000?? SignBits:6
+ ; CHECK-NEXT: %3:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
%0:_(s8) = G_CONSTANT i8 2
%1:_(s8) = G_CONSTANT i8 255
>From 1b927df72c3a8a3aaec285dc22ad7d14ddd931ec Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Wed, 10 Dec 2025 10:09:32 -0800
Subject: [PATCH 4/7] Add more tests for saddo
---
.../AArch64/GlobalISel/knownbits-saddo.mir | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
index 40c7e25ab943a..9fac33e341c13 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
@@ -27,3 +27,137 @@ body: |
%1:_(s8) = G_CONSTANT i8 126
%2:_(s8), %3:_(s1) = G_SADDO %0, %1
...
+---
+name: ScalarVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8), %3:_(s1) = G_SADDO %0, %1
+...
+---
+name: ScalarPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %3:_ KnownBits:00000101 SignBits:5
+ ; CHECK-NEXT: %4:_ KnownBits:000????? SignBits:3
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = G_CONSTANT i8 15
+ %2:_(s8) = G_AND %0, %1
+ %3:_(s8) = G_CONSTANT i8 5
+ %4:_(s8), %5:_(s1) = G_SADDO %2, %3
+...
+---
+name: VectorCstCarryOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0111110100000000 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:0111110100000000 SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:0111110100000010 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 32000
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_SADDO %2, %3
+...
+---
+name: VectorCstCarryOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0111111111111111 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:0111111111111111 SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:1000000000000001 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 32767
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_SADDO %2, %3
+...
+---
+name: VectorVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>), %3:_(<4 x s1>) = G_SADDO %0, %1
+...
+---
+name: VectorPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000101010 SignBits:10
+ ; CHECK-NEXT: %5:_ KnownBits:0000000001001010 SignBits:9
+ ; CHECK-NEXT: %6:_ KnownBits:000000000??01010 SignBits:9
+ ; CHECK-NEXT: %7:_ KnownBits:0000000????????? SignBits:7
+ ; CHECK-NEXT: %8:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = G_CONSTANT i16 255
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(<4 x s16>) = G_AND %0, %2
+ %4:_(s16) = G_CONSTANT i16 42
+ %5:_(s16) = G_CONSTANT i16 74
+ %6:_(<4 x s16>) = G_BUILD_VECTOR %4, %5, %5, %4
+ %7:_(<4 x s16>), %8:_(<4 x s1>) = G_SADDO %6, %3
+...
+---
+name: VectorCst36
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst36
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %4:_ KnownBits:000000000000???? SignBits:12
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 3
+ %1:_(s16) = G_CONSTANT i16 6
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_SADDO %2, %3
+...
+---
+name: VectorCst3unknown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst3unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = COPY $h0
+ %2:_(s16) = G_CONSTANT i16 3
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_SADDO %0, %3
+...
>From 5374267a77a16fac93098e9fade7ad3b4bf7a4ae Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Mon, 22 Dec 2025 15:42:23 -0800
Subject: [PATCH 5/7] Add more tests for uaddo
---
.../AArch64/GlobalISel/knownbits-uaddo.mir | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
index b10ea6c2926b3..28dc998c8fb87 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
@@ -27,3 +27,137 @@ body: |
%1:_(s8) = G_CONSTANT i8 254
%2:_(s8), %4:_(s1) = G_UADDO %0, %1
...
+---
+name: ScalarVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8), %3:_(s1) = G_UADDO %0, %1
+...
+---
+name: ScalarPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %3:_ KnownBits:00000101 SignBits:5
+ ; CHECK-NEXT: %4:_ KnownBits:000????? SignBits:3
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = G_CONSTANT i8 15
+ %2:_(s8) = G_AND %0, %1
+ %3:_(s8) = G_CONSTANT i8 5
+ %4:_(s8), %5:_(s1) = G_UADDO %2, %3
+...
+---
+name: VectorCstCarryOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:1111110111101000 SignBits:6
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:1111110111101000 SignBits:6
+ ; CHECK-NEXT: %4:_ KnownBits:1111110111101010 SignBits:6
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 65000
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_UADDO %2, %3
+...
+---
+name: VectorCstCarryOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:1111111111111111 SignBits:16
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:1111111111111111 SignBits:16
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000000001 SignBits:15
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 65535
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_UADDO %2, %3
+...
+---
+name: VectorVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>), %3:_(<4 x s1>) = G_UADDO %0, %1
+...
+---
+name: VectorPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000101010 SignBits:10
+ ; CHECK-NEXT: %5:_ KnownBits:0000000001001010 SignBits:9
+ ; CHECK-NEXT: %6:_ KnownBits:000000000??01010 SignBits:9
+ ; CHECK-NEXT: %7:_ KnownBits:0000000????????? SignBits:7
+ ; CHECK-NEXT: %8:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = G_CONSTANT i16 255
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(<4 x s16>) = G_AND %0, %2
+ %4:_(s16) = G_CONSTANT i16 42
+ %5:_(s16) = G_CONSTANT i16 74
+ %6:_(<4 x s16>) = G_BUILD_VECTOR %4, %5, %5, %4
+ %7:_(<4 x s16>), %8:_(<4 x s1>) = G_UADDO %6, %3
+...
+---
+name: VectorCst36
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst36
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %4:_ KnownBits:000000000000???? SignBits:12
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 3
+ %1:_(s16) = G_CONSTANT i16 6
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_UADDO %2, %3
+...
+---
+name: VectorCst3unknown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst3unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = COPY $h0
+ %2:_(s16) = G_CONSTANT i16 3
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_UADDO %0, %3
+...
>From 63827a29767c28a90e3880154a52a0ec5d1cc6d2 Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Mon, 22 Dec 2025 15:42:39 -0800
Subject: [PATCH 6/7] Add more tests for sadde
---
.../AArch64/GlobalISel/knownbits-sadde.mir | 212 ++++++++++++++++++
1 file changed, 212 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
index 8ba600b8a5ce1..90c3395264de5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
@@ -61,3 +61,215 @@ body: |
%2:_(s1) = G_CONSTANT i1 1
%3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
...
+---
+name: ScalarVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8) = COPY $b2
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s8), %5:_(s1) = G_SADDE %0, %1, %3
+...
+---
+name: ScalarPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %3:_ KnownBits:00000101 SignBits:5
+ ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:000????? SignBits:3
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = G_CONSTANT i8 15
+ %2:_(s8) = G_AND %0, %1
+ %3:_(s8) = G_CONSTANT i8 5
+ %4:_(s8) = COPY $b1
+ %5:_(s1) = G_TRUNC %4
+ %6:_(s8), %7:_(s1) = G_SADDE %2, %3, %5
+...
+---
+name: VectorCstCarryInZeroOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInZeroOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0111110100000000 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %4:_ KnownBits:0111110100000000 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:0111110100000010 SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 32000
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_SADDE %3, %4, %5
+...
+---
+name: VectorCstCarryInOneOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInOneOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0111110100000000 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %4:_ KnownBits:0111110100000000 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:0111110100000011 SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 32000
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_SADDE %3, %4, %5
+...
+---
+name: VectorCstCarryInZeroOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInZeroOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0111111111111111 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %4:_ KnownBits:0111111111111111 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:1000000000000001 SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 32767
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_SADDE %3, %4, %5
+...
+---
+name: VectorCstCarryInOneOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInOneOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
+ ; CHECK-NEXT: %1:_ KnownBits:0111111111111111 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000000 SignBits:16
+ ; CHECK-NEXT: %4:_ KnownBits:0111111111111111 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:1000000000000000 SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 0
+ %1:_(s16) = G_CONSTANT i16 32767
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_SADDE %3, %4, %5
+...
+---
+name: VectorVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s1>) = G_TRUNC %2
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_SADDE %0, %1, %3
+...
+---
+name: VectorPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000101010 SignBits:10
+ ; CHECK-NEXT: %5:_ KnownBits:0000000001001010 SignBits:9
+ ; CHECK-NEXT: %6:_ KnownBits:000000000??01010 SignBits:9
+ ; CHECK-NEXT: %7:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %8:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %9:_ KnownBits:0000000????????? SignBits:7
+ ; CHECK-NEXT: %10:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = G_CONSTANT i16 255
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(<4 x s16>) = G_AND %0, %2
+ %4:_(s16) = G_CONSTANT i16 42
+ %5:_(s16) = G_CONSTANT i16 74
+ %6:_(<4 x s16>) = G_BUILD_VECTOR %4, %5, %5, %4
+ %7:_(<4 x s16>) = COPY $d2
+ %8:_(<4 x s1>) = G_TRUNC %2
+ %9:_(<4 x s16>), %10:_(<4 x s1>) = G_SADDE %6, %3, %8
+...
+---
+name: VectorCst36
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst36
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %5:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %6:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:000000000000???? SignBits:12
+ ; CHECK-NEXT: %8:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 3
+ %1:_(s16) = G_CONSTANT i16 6
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s1) = G_CONSTANT i1 1
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %5:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %6:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %3, %3
+ %7:_(<4 x s16>), %8:_(<4 x s1>) = G_SADDE %4, %5, %6
+...
+---
+name: VectorCst3unknown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst3unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %8:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = COPY $h0
+ %2:_(s16) = G_CONSTANT i16 3
+ %3:_(s1) = G_CONSTANT i1 0
+ %4:_(s1) = G_CONSTANT i1 1
+ %5:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
+ %6:_(<4 x s1>) = G_BUILD_VECTOR %3, %3, %4, %4
+ %7:_(<4 x s16>), %8:_(<4 x s1>) = G_SADDE %0, %5, %6
+...
>From 25e5e74317e3af2cd5465422d31188a7e5fde3ae Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Mon, 22 Dec 2025 15:42:54 -0800
Subject: [PATCH 7/7] Add more tests for uadde
---
.../AArch64/GlobalISel/knownbits-uadde.mir | 212 ++++++++++++++++++
1 file changed, 212 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
index 1389816e507f7..9fcbfdf0ae311 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
@@ -61,3 +61,215 @@ body: |
%2:_(s1) = G_CONSTANT i1 1
%3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
...
+---
+name: ScalarVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8) = COPY $b2
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s8), %5:_(s1) = G_UADDE %0, %1, %3
+...
+---
+name: ScalarPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %3:_ KnownBits:00000101 SignBits:5
+ ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:000????? SignBits:3
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = G_CONSTANT i8 15
+ %2:_(s8) = G_AND %0, %1
+ %3:_(s8) = G_CONSTANT i8 5
+ %4:_(s8) = COPY $b1
+ %5:_(s1) = G_TRUNC %4
+ %6:_(s8), %7:_(s1) = G_UADDE %2, %3, %5
+...
+---
+name: VectorCstCarryInZeroOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInZeroOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:1111110111101000 SignBits:6
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %4:_ KnownBits:1111110111101000 SignBits:6
+ ; CHECK-NEXT: %5:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:1111110111101010 SignBits:6
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 65000
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_UADDE %3, %4, %5
+...
+---
+name: VectorCstCarryInOneOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInOneOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:1111110111101000 SignBits:6
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %4:_ KnownBits:1111110111101000 SignBits:6
+ ; CHECK-NEXT: %5:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:1111110111101011 SignBits:6
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 65000
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_UADDE %3, %4, %5
+...
+---
+name: VectorCstCarryInZeroOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInZeroOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:1111111111111111 SignBits:16
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000010 SignBits:14
+ ; CHECK-NEXT: %4:_ KnownBits:1111111111111111 SignBits:16
+ ; CHECK-NEXT: %5:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:0000000000000001 SignBits:15
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 2
+ %1:_(s16) = G_CONSTANT i16 65535
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_UADDE %3, %4, %5
+...
+---
+name: VectorCstCarryInOneOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCstCarryInOneOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
+ ; CHECK-NEXT: %1:_ KnownBits:1111111111111111 SignBits:16
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000000 SignBits:16
+ ; CHECK-NEXT: %4:_ KnownBits:1111111111111111 SignBits:16
+ ; CHECK-NEXT: %5:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:0000000000000000 SignBits:16
+ ; CHECK-NEXT: %7:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 0
+ %1:_(s16) = G_CONSTANT i16 65535
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %5:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
+ %6:_(<4 x s16>), %7:_(<4 x s1>) = G_UADDE %3, %4, %5
+...
+---
+name: VectorVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s1>) = G_TRUNC %2
+ %4:_(<4 x s16>), %5:_(<4 x s1>) = G_UADDE %0, %1, %3
+...
+---
+name: VectorPartKnown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorPartKnown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:0000000011111111 SignBits:8
+ ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000101010 SignBits:10
+ ; CHECK-NEXT: %5:_ KnownBits:0000000001001010 SignBits:9
+ ; CHECK-NEXT: %6:_ KnownBits:000000000??01010 SignBits:9
+ ; CHECK-NEXT: %7:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %8:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %9:_ KnownBits:0000000????????? SignBits:7
+ ; CHECK-NEXT: %10:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = G_CONSTANT i16 255
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(<4 x s16>) = G_AND %0, %2
+ %4:_(s16) = G_CONSTANT i16 42
+ %5:_(s16) = G_CONSTANT i16 74
+ %6:_(<4 x s16>) = G_BUILD_VECTOR %4, %5, %5, %4
+ %7:_(<4 x s16>) = COPY $d2
+ %8:_(<4 x s1>) = G_TRUNC %2
+ %9:_(<4 x s16>), %10:_(<4 x s1>) = G_UADDE %6, %3, %8
+...
+---
+name: VectorCst36
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst36
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %5:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %6:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:000000000000???? SignBits:12
+ ; CHECK-NEXT: %8:_ KnownBits:? SignBits:1
+ %0:_(s16) = G_CONSTANT i16 3
+ %1:_(s16) = G_CONSTANT i16 6
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s1) = G_CONSTANT i1 1
+ %4:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %5:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %6:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %3, %3
+ %7:_(<4 x s16>), %8:_(<4 x s1>) = G_UADDE %4, %5, %6
+...
+---
+name: VectorCst3unknown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst3unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %5:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %6:_ KnownBits:? SignBits:1
+ ; CHECK-NEXT: %7:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %8:_ KnownBits:? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = COPY $h0
+ %2:_(s16) = G_CONSTANT i16 3
+ %3:_(s1) = G_CONSTANT i1 0
+ %4:_(s1) = G_CONSTANT i1 1
+ %5:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
+ %6:_(<4 x s1>) = G_BUILD_VECTOR %3, %3, %4, %4
+ %7:_(<4 x s16>), %8:_(<4 x s1>) = G_UADDE %0, %5, %6
+...
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