[llvm] [Mips] Custom lowering of SET_ROUNDING, GET_ROUNDING (PR #170047)

[Erik Enikeev via llvm-commits]

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@@ -62,6 +65,10 @@ def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
 
 // Node used to generate an MTC1 i32 to f64 instruction
 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
+def MipsReadFCSR : SDNode<"MipsISD::ReadFCSR", SDT_MipsReadFCSR,
+                             [SDNPHasChain]>;
+def MipsWriteFCSR : SDNode<"MipsISD::WriteFCSR", SDT_MipsWriteFCSR,
+                              [SDNPHasChain, SDNPSideEffect]>;
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Varnike wrote:

Maybe I didn't write it very clearly, but what I mean is that to correctly model the rounding mode bits, dependencies on the `FCR31` (`FCSR`) register are used, rather than tracking of individual bits. FP instructions which use rounding mode are marked as using `FCR31`, therefore they will be correctly ordered with operations that may modify this register. 

> However, with the current implementation, separating this register from the rest of the fcr register class will not be entirely straightforward.

At the moment, `FCR31` is not separated from the other FCR registers in any way and all instructions operate on `CCROpnd` (`FCR0`-`FCR31`). So, if we would choose this approach:

> using MachineNode to directly use CFC1/CTC1 in the lowering, it would be sufficient to set Uses/Defs only for FCR31 on these instructions

then we will need to separate the `FCR31` register from `CCROpnd` in order to correctly mark operations that access it  (e.g. setting Uses = [FCR31] for CFC1 and Defs = [FCR31] for CTC1).

>These pseudos aren't really helping

Current implementation uses pseudos to address this issue by assigning Uses/Defs of `FCR31` to the pseudos, without modifying the existing instructions. Perhaps I misunderstood your comment on pseudos, in which case please let me know.

https://github.com/llvm/llvm-project/pull/170047