[llvm] [llvm][RISCV] Support rounding mulh for P extension codegen (PR #171593)

[Craig Topper via llvm-commits]

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@@ -16401,14 +16426,24 @@ static SDValue combinePExtTruncate(SDNode *N, SelectionDAG &DAG,
       return SDValue();
     break;
   case ISD::MUL:
-    // PMULHSU: shift amount must be element size, only for i16/i32
-    unsigned EltBits = VecVT.getScalarSizeInBits();
+    // PMULH*/PMULHR*: shift amount must be element size, only for i16/i32
     if (ShAmtVal != EltBits || (EltBits != 16 && EltBits != 32))
       return SDValue();
-    if (LHSIsSExt && RHSIsZExt)
-      Opc = RISCVISD::PMULHSU;
-    else
-      return SDValue();
+    if (IsRounding) {
+      if (LHSIsSExt && RHSIsSExt)
+        Opc = RISCVISD::PMULHR;
+      else if (LHSIsZExt && RHSIsZExt)
+        Opc = RISCVISD::PMULHRU;
+      else if (LHSIsSExt && RHSIsZExt)
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topperc wrote:

What about the commuted case?

https://github.com/llvm/llvm-project/pull/171593