[llvm] [Mips] Custom lowering of SET_ROUNDING, GET_ROUNDING (PR #170047)

[Erik Enikeev via llvm-commits]

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@@ -62,6 +65,10 @@ def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
 
 // Node used to generate an MTC1 i32 to f64 instruction
 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
+def MipsReadFCSR : SDNode<"MipsISD::ReadFCSR", SDT_MipsReadFCSR,
+                             [SDNPHasChain]>;
+def MipsWriteFCSR : SDNode<"MipsISD::WriteFCSR", SDT_MipsWriteFCSR,
+                              [SDNPHasChain, SDNPSideEffect]>;
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Varnike wrote:

This is done to correctly set `FCSR` (`FCR31`) register uses/defs, which is required for proper modelling of reads/writes of the rounding control bits. In my understanding, when using `MachineNode` in the lowering, it would be sufficient to set Uses/Defs only for `FCR31` on `CFC1`/`CTC1` instructions. However, with the current implementation, separating this register from the rest of the fcr register class will not be entirely straightforward. What would be the best approach here?

https://github.com/llvm/llvm-project/pull/170047