[llvm] [AArch64][SDAG] Select extractelement <vscale x 1 x i1> (PR #173016)

[Paul Walker via llvm-commits]

================
@@ -16300,10 +16300,18 @@ AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
   EVT VT = Op.getOperand(0).getValueType();
 
   if (VT.getScalarType() == MVT::i1) {
+    SDLoc DL(Op);
+    // There are no operations to extend a nxv1i1 predicate to a nxv1i128 vector
+    // An easy lowering is widening the input predicate to nxv2i1.
+    if (VT.getVectorElementCount() == ElementCount::getScalable(1)) {
----------------
paulwalker-arm wrote:

```suggestion
    if (VT == MVT::nxv1i1) {
```

https://github.com/llvm/llvm-project/pull/173016