[llvm] [MCA][AArch64] Model single-register EXTR as ROR on Neoverse N2 (PR #172831)
Amina Chabane via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 22 05:59:55 PST 2025
https://github.com/Amichaxx updated https://github.com/llvm/llvm-project/pull/172831
>From e74cce00440c98c220d44834ce31824c15fdc2e1 Mon Sep 17 00:00:00 2001
From: Amichaxx <amina.chabane at arm.com>
Date: Wed, 17 Dec 2025 14:44:42 +0000
Subject: [PATCH 1/2] [MCA][AArch64] Model single-register EXTR as ROR on
Neoverse N2
---
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td | 10 ++++++----
.../AArch64/Neoverse/N2-basic-instructions.s | 14 +++++++-------
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index a02130f8390a7..f30f38fbd09d0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -664,6 +664,10 @@ def N2Write_0or3c_1M0 : SchedWriteVariant<[
SchedVar<NeoverseZeroMove, [N2Write_0c]>,
SchedVar<NoSchedPred, [N2Write_3c_1M0]>]>;
+def N2Write_Extr : SchedWriteVariant<[
+ SchedVar<IsRORImmIdiomPred, [N2Write_1c_1I]>,
+ SchedVar<NoSchedPred, [N2Write_3c_1I_1M]>]>;
+
//===----------------------------------------------------------------------===//
// Define types for arithmetic and logical ops with short shifts
def N2Write_Arith : SchedWriteVariant<[
@@ -779,10 +783,8 @@ def : InstRW<[N2Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;
// Bitfield extract, one reg
// Bitfield extract, two regs
-// NOTE: We don't model the difference between EXTR where both operands are the
-// same (one reg).
-def : SchedAlias<WriteExtr, N2Write_3c_1I_1M>;
-def : InstRW<[N2Write_3c_1I_1M], (instrs EXTRWrri, EXTRXrri)>;
+def : SchedAlias<WriteExtr, N2Write_Extr>;
+def : InstRW<[N2Write_Extr], (instrs EXTRWrri, EXTRXrri)>;
// Bitfield move, basic
def : SchedAlias<WriteIS, N2Write_1c_1I>;
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
index 18c853c2427a6..46b669b52dcc4 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
@@ -502,9 +502,9 @@
# CHECK-NEXT: 2 3 0.50 extr w11, w13, w17, #31
# CHECK-NEXT: 2 3 0.50 extr x3, x5, x7, #15
# CHECK-NEXT: 2 3 0.50 extr x11, x13, x17, #63
-# CHECK-NEXT: 2 3 0.50 ror x19, x23, #24
-# CHECK-NEXT: 2 3 0.50 ror x29, xzr, #63
-# CHECK-NEXT: 2 3 0.50 ror w9, w13, #31
+# CHECK-NEXT: 1 1 0.25 ror x19, x23, #24
+# CHECK-NEXT: 1 1 0.25 ror x29, xzr, #63
+# CHECK-NEXT: 1 1 0.25 ror w9, w13, #31
# CHECK-NEXT: 1 2 1.00 fcmp h5, h21
# CHECK-NEXT: 1 2 1.00 fcmp h5, #0.0
# CHECK-NEXT: 1 2 1.00 fcmpe h22, h21
@@ -1267,7 +1267,7 @@
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8]
-# CHECK-NEXT: 13.00 13.00 34.00 34.00 90.33 161.33 161.33 539.50 253.50 169.00 169.00 254.00 101.00
+# CHECK-NEXT: 13.00 13.00 34.00 34.00 90.33 161.33 161.33 538.00 252.00 169.00 169.00 254.00 101.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions:
@@ -1763,9 +1763,9 @@
# CHECK-NEXT: - - - - - - - 0.75 0.75 0.25 0.25 - - extr w11, w13, w17, #31
# CHECK-NEXT: - - - - - - - 0.75 0.75 0.25 0.25 - - extr x3, x5, x7, #15
# CHECK-NEXT: - - - - - - - 0.75 0.75 0.25 0.25 - - extr x11, x13, x17, #63
-# CHECK-NEXT: - - - - - - - 0.75 0.75 0.25 0.25 - - ror x19, x23, #24
-# CHECK-NEXT: - - - - - - - 0.75 0.75 0.25 0.25 - - ror x29, xzr, #63
-# CHECK-NEXT: - - - - - - - 0.75 0.75 0.25 0.25 - - ror w9, w13, #31
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - ror x19, x23, #24
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - ror x29, xzr, #63
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - ror w9, w13, #31
# CHECK-NEXT: - - - - - - - - - - - 1.00 - fcmp h5, h21
# CHECK-NEXT: - - - - - - - - - - - 1.00 - fcmp h5, #0.0
# CHECK-NEXT: - - - - - - - - - - - 1.00 - fcmpe h22, h21
>From 88076a4865317de088be2d174dcb1e884c789471 Mon Sep 17 00:00:00 2001
From: Amichaxx <amina.chabane at arm.com>
Date: Mon, 22 Dec 2025 10:14:09 +0000
Subject: [PATCH 2/2] Comments addressing
---
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index f30f38fbd09d0..87d387698ad15 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -784,7 +784,6 @@ def : InstRW<[N2Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;
// Bitfield extract, one reg
// Bitfield extract, two regs
def : SchedAlias<WriteExtr, N2Write_Extr>;
-def : InstRW<[N2Write_Extr], (instrs EXTRWrri, EXTRXrri)>;
// Bitfield move, basic
def : SchedAlias<WriteIS, N2Write_1c_1I>;
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