[llvm] [AMDGPU] siloadstoreopt generate REG_SEQUENCE with aligned operands (PR #162088)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,29 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -start-before=si-load-store-opt %s -o - | FileCheck %s
+
+# CHECK-LABEL: misaligned_vgpr:
+# CHECK: ; %bb.0:
+# CHECK:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+# CHECK:         v_mov_b64_e32 v[0:1], 0
+# CHECK:         v_mov_b32_e32 v2, 0
+# CHECK:         v_mov_b32_e32 v3, v0
+# CHECK:         v_mov_b32_e32 v4, v1
+# CHECK:         flat_store_dwordx3 v[0:1], v[2:4]
+# CHECK:         s_endpgm
+
+--- |
+  define void @misaligned_vgpr() { ret void }
+...
+
+---
+name: misaligned_vgpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %10:vreg_64_align2 = IMPLICIT_DEF
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arsenm wrote:

Compact register numbers (can use -run-pass=none) 

https://github.com/llvm/llvm-project/pull/162088