[llvm] [AMDGPU] Allow allocation of lo128 registers from all banks (PR #172614)

[Quentin Colombet via llvm-commits]

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@@ -813,7 +813,11 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
           OpInfo, STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo));
       const MCRegisterClass &RC = MRI.getRegClass(RCID);
       auto Reg = mc2PseudoReg(Op.getReg());
-      if (!RC.contains(Reg) && !isInlineValue(Reg)) {
+      bool Err = !RC.contains(Reg) && !isInlineValue(Reg);
+      if (!Err && (RCID == AMDGPU::VGPR_32_Lo128RegClassID ||
+                   RCID == AMDGPU::VS_32_Lo128RegClassID))
+        Err = Reg >= AMDGPU::VGPR128 && Reg <= AMDGPU::VGPR1023;
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qcolombet wrote:

>  it can also accept SGPRs.

Ah gotcha.
Thanks for pointing this out.

However, shouldn't the check here still be consistent with what we check in the added lines at 2251 in AMDGPUAsmParser (except reversed: `Err = !AMDGPU::isNotHi128VGPR32(Reg);`)

https://github.com/llvm/llvm-project/pull/172614