[llvm] [RISCV] Enable PACK isel patterns for P extension. (PR #173064)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/173064.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZb.td (+4-2) 
- (modified) llvm/test/CodeGen/RISCV/rv32p.ll (+37) 
- (modified) llvm/test/CodeGen/RISCV/rv64p.ll (+39) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 0eee6b5e90fc9..129e392baa02d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -648,10 +648,11 @@ def : Pat<(shl (and GPR:$rs2, 0xFF), (XLenVT 8)),
           (PACKH (XLenVT X0), GPR:$rs2)>;
 } // Predicates = [HasStdExtZbkb]
 
-let Predicates = [HasStdExtZbkb, IsRV32] in {
+let Predicates = [HasStdExtZbkbOrP, IsRV32] in
 def : Pat<(i32 (or zexti16:$rs1, (shl GPR:$rs2, (i32 16)))),
           (PACK zexti16:$rs1, GPR:$rs2)>;
 
+let Predicates = [HasStdExtZbkb, IsRV32] in {
 def : Pat<(i32 (or (shl GPR:$rs2, (XLenVT 24)),
                    (shl zexti8:$rs1, (XLenVT 16)))),
           (SLLI (XLenVT (PACKH zexti8:$rs1, GPR:$rs2)), (XLenVT 16))>;
@@ -667,10 +668,11 @@ def : Pat<(i32 (or (or (shl GPR:$op1rs2, (XLenVT 24)),
                 (XLenVT (PACKH zexti8:$op1rs1, GPR:$op1rs2)))>;
 }
 
-let Predicates = [HasStdExtZbkb, IsRV64] in {
+let Predicates = [HasStdExtZbkbOrP, IsRV64] in
 def : Pat<(i64 (or zexti32:$rs1, (shl GPR:$rs2, (i64 32)))),
           (PACK zexti32:$rs1, GPR:$rs2)>;
 
+let Predicates = [HasStdExtZbkb, IsRV64] in {
 def : Pat<(i64 (or (shl zexti8:$rs2, (XLenVT 24)),
                    (shl zexti8:$rs1, (XLenVT 16)))),
           (SLLI (XLenVT (PACKH zexti8:$rs1, zexti8:$rs2)), (XLenVT 16))>;
diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll
index 0d543e385ea00..dc247e2f8bf67 100644
--- a/llvm/test/CodeGen/RISCV/rv32p.ll
+++ b/llvm/test/CodeGen/RISCV/rv32p.ll
@@ -45,3 +45,40 @@ define void @pli_b_store_i32(ptr %p) {
   store i32 u0x41414141, ptr %p
   ret void
 }
+
+define i32 @pack_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: pack_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pack a0, a0, a1
+; CHECK-NEXT:    ret
+  %shl = and i32 %a, 65535
+  %shl1 = shl i32 %b, 16
+  %or = or i32 %shl1, %shl
+  ret i32 %or
+}
+
+define i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {
+; CHECK-LABEL: pack_i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pack a0, a0, a1
+; CHECK-NEXT:    ret
+  %zexta = zext i16 %a to i32
+  %zextb = zext i16 %b to i32
+  %shl1 = shl i32 %zextb, 16
+  %or = or i32 %shl1, %zexta
+  ret i32 %or
+}
+
+define i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 %2) {
+; CHECK-LABEL: pack_i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pack a0, a1, a0
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    ret
+  %4 = zext i16 %0 to i32
+  %5 = shl nuw i32 %4, 16
+  %6 = zext i16 %1 to i32
+  %7 = or i32 %5, %6
+  %8 = add i32 %7, %2
+  ret i32 %8
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
index bff9771299a88..956970ac2a9e0 100644
--- a/llvm/test/CodeGen/RISCV/rv64p.ll
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -57,3 +57,42 @@ define void @pli_b_store_i32(ptr %p) {
   store i32 u0x41414141, ptr %p
   ret void
 }
+
+define i64 @pack_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: pack_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pack a0, a0, a1
+; CHECK-NEXT:    ret
+  %shl = and i64 %a, 4294967295
+  %shl1 = shl i64 %b, 32
+  %or = or i64 %shl1, %shl
+  ret i64 %or
+}
+
+define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: pack_i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pack a0, a0, a1
+; CHECK-NEXT:    ret
+  %zexta = zext i32 %a to i64
+  %zextb = zext i32 %b to i64
+  %shl1 = shl i64 %zextb, 32
+  %or = or i64 %shl1, %zexta
+  ret i64 %or
+}
+
+define i64 @pack_i64_3(ptr %0, ptr %1) {
+; CHECK-LABEL: pack_i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    lw a1, 0(a1)
+; CHECK-NEXT:    pack a0, a1, a0
+; CHECK-NEXT:    ret
+  %3 = load i32, ptr %0, align 4
+  %4 = zext i32 %3 to i64
+  %5 = shl i64 %4, 32
+  %6 = load i32, ptr %1, align 4
+  %7 = zext i32 %6 to i64
+  %8 = or i64 %5, %7
+  ret i64 %8
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/173064