[llvm] [PowerPC] Add type checking for DMF insert 512 (PR #172078)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 19 08:11:30 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: None (RolandF77)
<details>
<summary>Changes</summary>
Create PPCISD node for DMF DMXXINSTDMR512 operations to allow type checking.
---
Patch is 90.42 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/172078.diff
11 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+18-25)
- (modified) llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td (+29-3)
- (modified) llvm/test/CodeGen/PowerPC/dmf-outer-product.ll (+280-280)
- (modified) llvm/test/CodeGen/PowerPC/dmr-enable.ll (+43-43)
- (modified) llvm/test/CodeGen/PowerPC/dmr-spill.ll (+24-24)
- (modified) llvm/test/CodeGen/PowerPC/dmrp-spill.ll (+30-30)
- (modified) llvm/test/CodeGen/PowerPC/mma-intrinsics.ll (+12-12)
- (modified) llvm/test/CodeGen/PowerPC/mma-outer-product.ll (+48-48)
- (modified) llvm/test/CodeGen/PowerPC/mmaplus-crypto.ll (+44-44)
- (modified) llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll (+8-8)
- (modified) llvm/test/CodeGen/PowerPC/v1024ls.ll (+6-6)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index addb47a69f5ff..c58ecbf105290 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11234,14 +11234,14 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
unsigned Opcode;
unsigned Subx;
if (HiLo == 0) {
- Opcode = PPC::DMXXINSTDMR512;
+ Opcode = PPCISD::INST512;
Subx = PPC::sub_wacc_lo;
} else {
- Opcode = PPC::DMXXINSTDMR512_HI;
+ Opcode = PPCISD::INST512HI;
Subx = PPC::sub_wacc_hi;
}
- SDValue Ops[] = {Op.getOperand(2), Op.getOperand(3)};
- SDValue Wacc = SDValue(DAG.getMachineNode(Opcode, dl, MVT::v512i1, Ops), 0);
+ SDValue Wacc = DAG.getNode(Opcode, dl, MVT::v512i1, Op.getOperand(2),
+ Op.getOperand(3));
SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
return SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl, MVT::v1024i1,
Op.getOperand(1), Wacc, SubReg),
@@ -11271,9 +11271,8 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
}
SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
SDValue P = DAG.getTargetConstant(IdxVal, dl, MVT::i32);
- SDValue Ops[] = {Op.getOperand(2), P};
- SDValue DMRRowp = SDValue(
- DAG.getMachineNode(PPC::DMXXINSTDMR256, dl, MVT::v256i1, Ops), 0);
+ SDValue DMRRowp =
+ DAG.getNode(PPCISD::INST256, dl, MVT::v256i1, Op.getOperand(2), P);
return SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl, MVT::v1024i1,
Op.getOperand(1), DMRRowp, SubReg),
0);
@@ -12012,13 +12011,11 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
}
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
- SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Loads[0],
- Loads[1]),
- 0);
+ SDValue Lo =
+ DAG.getNode(PPCISD::INST512, dl, MVT::v512i1, Loads[0], Loads[1]);
SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
- SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
- Loads[2], Loads[3]),
- 0);
+ SDValue Hi =
+ DAG.getNode(PPCISD::INST512HI, dl, MVT::v512i1, Loads[2], Loads[3]);
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
SDValue RC = DAG.getTargetConstant(PPC::DMRRCRegClassID, dl, MVT::i32);
const SDValue Ops[] = {RC, Lo, LoSub, Hi, HiSub};
@@ -12032,12 +12029,10 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
// Handle Loads for V2048i1 which represents a dmr pair.
SDValue DmrPValue;
- SDValue Dmr1Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1,
- Loads[4], Loads[5]),
- 0);
- SDValue Dmr1Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
- Loads[6], Loads[7]),
- 0);
+ SDValue Dmr1Lo =
+ DAG.getNode(PPCISD::INST512, dl, MVT::v512i1, Loads[4], Loads[5]);
+ SDValue Dmr1Hi =
+ DAG.getNode(PPCISD::INST512HI, dl, MVT::v512i1, Loads[6], Loads[7]);
const SDValue Dmr1Ops[] = {RC, Dmr1Lo, LoSub, Dmr1Hi, HiSub};
SDValue Dmr1Value = SDValue(
DAG.getMachineNode(PPC::REG_SEQUENCE, dl, MVT::v1024i1, Dmr1Ops), 0);
@@ -12057,13 +12052,11 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
SDValue PPCTargetLowering::DMFInsert1024(const SmallVectorImpl<SDValue> &Pairs,
const SDLoc &dl,
SelectionDAG &DAG) const {
- SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Pairs[0],
- Pairs[1]),
- 0);
+ SDValue Lo =
+ DAG.getNode(PPCISD::INST512, dl, MVT::v512i1, Pairs[0], Pairs[1]);
SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
- SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
- Pairs[2], Pairs[3]),
- 0);
+ SDValue Hi =
+ DAG.getNode(PPCISD::INST512HI, dl, MVT::v512i1, Pairs[2], Pairs[3]);
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
SDValue RC = DAG.getTargetConstant(PPC::DMRRCRegClassID, dl, MVT::i32);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 8848957937525..076c7465994cf 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -12,6 +12,27 @@
//
//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// PowerPC ISA Future specific type constraints.
+//
+
+def SDT_PPCInst512 : SDTypeProfile<1, 2, [
+ SDTCisVT<0, v512i1>, SDTCisVT<1, v256i1>, SDTCisVT<2, v256i1>
+]>;
+def SDT_PPCInst256 : SDTypeProfile<1, 2, [
+ SDTCisVT<0, v256i1>, SDTCisVT<1, v256i1>, SDTCisVT<2, i32>
+]>;
+
+//===----------------------------------------------------------------------===//
+// ISA Future specific PPCISD nodes.
+//
+
+def PPCInst512 : SDNode<"PPCISD::INST512", SDT_PPCInst512, []>;
+def PPCInst512Hi : SDNode<"PPCISD::INST512HI", SDT_PPCInst512, []>;
+def PPCInst256 : SDNode<"PPCISD::INST256", SDT_PPCInst256, []>;
+
+//===----------------------------------------------------------------------===//
+
class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
@@ -429,14 +450,18 @@ let Predicates = [MMA, IsISAFuture] in {
def DMXXINSTDMR512
: XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
- "dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> {
+ "dmxxinstdmr512 $AT, $XAp, $XBp, 0",
+ [(set v512i1:$AT, (PPCInst512 v256i1:$XAp,
+ v256i1:$XBp))]> {
let P = 0;
}
def DMXXINSTDMR512_HI
: XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
- "dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> {
+ "dmxxinstdmr512 $AT, $XAp, $XBp, 1",
+ [(set v512i1:$AT, (PPCInst512Hi v256i1:$XAp,
+ v256i1:$XBp))]> {
let P = 1;
}
@@ -446,7 +471,8 @@ let Predicates = [MMA, IsISAFuture] in {
def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
(ins vsrprc:$XBp, u2imm:$P),
- "dmxxinstdmr256 $AT, $XBp, $P", []>;
+ "dmxxinstdmr256 $AT, $XBp, $P",
+ [(set v256i1:$AT, (PPCInst256 v256i1:$XBp, timm:$P))]>;
def DMMR
: XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB), "dmmr $AT, $AB",
diff --git a/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll b/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
index 4dccbf2d2cc1d..ebdc4390bac28 100644
--- a/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
+++ b/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
@@ -51,14 +51,14 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-NEXT: lxvp vsp34, 64(r3)
-; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: lxv v2, 16(r4)
+; CHECK-NEXT: lxvp vsp32, 64(r3)
+; CHECK-NEXT: lxvp vsp38, 96(r3)
+; CHECK-NEXT: lxv v8, 16(r4)
+; CHECK-NEXT: lxv v9, 0(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
-; CHECK-NEXT: lxv v3, 0(r4)
-; CHECK-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs0
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-NEXT: dmxvi8gerx4pp dmr0, vsp40, vs0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -71,14 +71,14 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
+; CHECK-BE-NEXT: lxv v8, 0(r4)
+; CHECK-BE-NEXT: lxv v9, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
-; CHECK-BE-NEXT: lxv v3, 16(r4)
-; CHECK-BE-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-BE-NEXT: dmxvi8gerx4pp dmr0, vsp40, vs0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -102,14 +102,14 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-NEXT: lxvp vsp34, 64(r3)
-; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: lxv v2, 16(r4)
+; CHECK-NEXT: lxvp vsp32, 64(r3)
+; CHECK-NEXT: lxvp vsp38, 96(r3)
+; CHECK-NEXT: lxv v8, 16(r4)
+; CHECK-NEXT: lxv v9, 0(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
-; CHECK-NEXT: lxv v3, 0(r4)
-; CHECK-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-NEXT: dmxvi8gerx4spp dmr0, vsp40, vs0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -122,14 +122,14 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
+; CHECK-BE-NEXT: lxv v8, 0(r4)
+; CHECK-BE-NEXT: lxv v9, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
-; CHECK-BE-NEXT: lxv v3, 16(r4)
-; CHECK-BE-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-BE-NEXT: dmxvi8gerx4spp dmr0, vsp40, vs0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -153,14 +153,14 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-NEXT: lxvp vsp34, 64(r3)
-; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: lxv v2, 16(r4)
+; CHECK-NEXT: lxvp vsp32, 64(r3)
+; CHECK-NEXT: lxvp vsp38, 96(r3)
+; CHECK-NEXT: lxv v8, 16(r4)
+; CHECK-NEXT: lxv v9, 0(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
-; CHECK-NEXT: lxv v3, 0(r4)
-; CHECK-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-NEXT: pmdmxvi8gerx4pp dmr0, vsp40, vs0, 42, 7, 9
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -173,14 +173,14 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
+; CHECK-BE-NEXT: lxv v8, 0(r4)
+; CHECK-BE-NEXT: lxv v9, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
-; CHECK-BE-NEXT: lxv v3, 16(r4)
-; CHECK-BE-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-BE-NEXT: pmdmxvi8gerx4pp dmr0, vsp40, vs0, 42, 7, 9
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -242,14 +242,14 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-NEXT: lxvp vsp34, 64(r3)
-; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: lxv v2, 16(r4)
+; CHECK-NEXT: lxvp vsp32, 64(r3)
+; CHECK-NEXT: lxvp vsp38, 96(r3)
+; CHECK-NEXT: lxv v8, 16(r4)
+; CHECK-NEXT: lxv v9, 0(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
-; CHECK-NEXT: lxv v3, 0(r4)
-; CHECK-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-NEXT: pmdmxvi8gerx4spp dmr0, vsp40, vs0, 100, 6, 12
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -262,14 +262,14 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
+; CHECK-BE-NEXT: lxv v8, 0(r4)
+; CHECK-BE-NEXT: lxv v9, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
-; CHECK-BE-NEXT: lxv v3, 16(r4)
-; CHECK-BE-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-BE-NEXT: pmdmxvi8gerx4spp dmr0, vsp40, vs0, 100, 6, 12
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -331,14 +331,14 @@ define void @test_dmxvbf16gerx2pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-NEXT: lxvp vsp34, 64(r3)
-; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: lxv v2, 16(r4)
+; CHECK-NEXT: lxvp vsp32, 64(r3)
+; CHECK-NEXT: lxvp vsp38, 96(r3)
+; CHECK-NEXT: lxv v8, 16(r4)
+; CHECK-NEXT: lxv v9, 0(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
-; CHECK-NEXT: lxv v3, 0(r4)
-; CHECK-NEXT: dmxvbf16gerx2pp dmr0, vsp34, vs0
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-NEXT: dmxvbf16gerx2pp dmr0, vsp40, vs0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -351,14 +351,14 @@ define void @test_dmxvbf16gerx2pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
+; CHECK-BE-NEXT: lxv v8, 0(r4)
+; CHECK-BE-NEXT: lxv v9, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
-; CHECK-BE-NEXT: lxv v3, 16(r4)
-; CHECK-BE-NEXT: dmxvbf16gerx2pp dmr0, vsp34, vs0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-BE-NEXT: dmxvbf16gerx2pp dmr0, vsp40, vs0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -382,14 +382,14 @@ define void @test_dmxvbf16gerx2pn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-NEXT: lxvp vsp34, 64(r3)
-; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: lxv v2, 16(r4)
+; CHECK-NEXT: lxvp vsp32, 64(r3)
+; CHECK-NEXT: lxvp vsp38, 96(r3)
+; CHECK-NEXT: lxv v8, 16(r4)
+; CHECK-NEXT: lxv v9, 0(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
-; CHECK-NEXT: lxv v3, 0(r4)
-; CHECK-NEXT: dmxvbf16gerx2pn dmr0, vsp34, vs0
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-NEXT: dmxvbf16gerx2pn dmr0, vsp40, vs0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -402,14 +402,14 @@ define void @test_dmxvbf16gerx2pn(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
-; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-BE-NEXT: lxv v2, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
+; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
+; CHECK-BE-NEXT: lxv v8, 0(r4)
+; CHECK-BE-NEXT: lxv v9, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
-; CHECK-BE-NEXT: lxv v3, 16(r4)
-; CHECK-BE-NEXT: dmxvbf16gerx2pn dmr0, vsp34, vs0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-BE-NEXT: dmxvbf16gerx2pn dmr0, vsp40, vs0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -433,14 +433,14 @@ define void @test_dmxvbf16gerx2np(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
-; CHECK-NEXT: lxvp vsp34, 64(r3)
-; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: lxv v2, 16(r4)
+; CHECK-NEXT: lxvp vsp32, 64(r3)
+; CHECK-NEXT: lxvp vsp38, 96(r3)
+; CHECK-NEXT: lxv v8, 16(r4)
+; CHECK-NEXT: lxv v9, 0(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
-; CHECK-NEXT: lxv v3, 0(r4)
-; CHEC...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/172078
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