[llvm] [AArch64][ISel] Extend insertelement tests (PR #173003)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 19 06:27:56 PST 2025
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/173003 at github.com>
================
@@ -165,31 +165,378 @@ define <vscale x 16 x i8> @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) {
ret <vscale x 16 x i8> %b
}
+; TODO: Implement DAG combiner.
+; INSERT_VECTOR_ELT(poison, ...) -> VECTOR_SPLAT
-; Redundant lane insert
-define <vscale x 4 x i32> @extract_insert_4xi32(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: extract_insert_4xi32:
+define <vscale x 16 x i8> @test_lanex_16xi8_poison(i8 %e, i32 %x) {
+; CHECK-LABEL: test_lanex_16xi8_poison:
; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.b, #0, #1
+; CHECK-NEXT: mov w8, w1
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z1.b, w8
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: mov z0.b, p0/m, w0
; CHECK-NEXT: ret
- %b = extractelement <vscale x 4 x i32> %a, i32 2
- %c = insertelement <vscale x 4 x i32> %a, i32 %b, i32 2
- ret <vscale x 4 x i32> %c
+ %b = insertelement <vscale x 16 x i8> poison, i8 %e, i32 %x
+ ret <vscale x 16 x i8> %b
}
-define <vscale x 8 x i16> @test_lane6_undef_8xi16(i16 %a) {
-; CHECK-LABEL: test_lane6_undef_8xi16:
+define <vscale x 16 x i8> @test_lanex_16xi8_poison_imm(i8 %e, i32 %x) {
+; CHECK-LABEL: test_lanex_16xi8_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.b, #0, #1
+; CHECK-NEXT: mov w8, w1
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z1.b, w8
+; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: mov z0.b, p0/m, w8
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 16 x i8> poison, i8 5, i32 %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 8 x i16> @test_lanex_8xi16_poison(i16 %e, i32 %x) {
+; CHECK-LABEL: test_lanex_8xi16_poison:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: index z0.h, #0, #1
+; CHECK-NEXT: mov w8, w1
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h
; CHECK-NEXT: mov z0.h, p0/m, w0
; CHECK-NEXT: ret
- %b = insertelement <vscale x 8 x i16> poison, i16 %a, i32 6
+ %b = insertelement <vscale x 8 x i16> poison, i16 %e, i32 %x
ret <vscale x 8 x i16> %b
}
+define <vscale x 8 x i16> @test_lanex_8xi16_poison_imm(i32 %x) {
+; CHECK-LABEL: test_lanex_8xi16_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.h, #0, #1
+; CHECK-NEXT: mov w8, w0
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z1.h, w8
+; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: mov z0.h, p0/m, w8
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 8 x i16> poison, i16 5, i32 %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 4 x i32> @test_lanex_4xi32_poison(i32 %e, i32 %x) {
+; CHECK-LABEL: test_lanex_4xi32_poison:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.s, #0, #1
+; CHECK-NEXT: mov w8, w1
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z1.s, w8
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: mov z0.s, p0/m, w0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 4 x i32> poison, i32 %e, i32 %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 4 x i32> @test_lanex_4xi32_poison_imm(i32 %x) {
+; CHECK-LABEL: test_lanex_4xi32_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.s, #0, #1
+; CHECK-NEXT: mov w8, w0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z1.s, w8
+; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: mov z0.s, p0/m, w8
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 4 x i32> poison, i32 5, i32 %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 2 x i64> @test_lanex_2xi64_poison(i64 %e, i32 %x) {
+; CHECK-LABEL: test_lanex_2xi64_poison:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.d, #0, #1
+; CHECK-NEXT: mov w8, w1
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: mov z1.d, x8
+; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: mov z0.d, p0/m, x0
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 2 x i64> poison, i64 %e, i32 %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 2 x i64> @test_lanex_2xi64_poison_imm(i32 %x) {
+; CHECK-LABEL: test_lanex_2xi64_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.d, #0, #1
+; CHECK-NEXT: mov w8, w0
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: mov z1.d, x8
+; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: mov z0.d, p0/m, x8
+; CHECK-NEXT: ret
+ %b = insertelement <vscale x 2 x i64> poison, i64 5, i32 %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 2 x half> @test_lanex_nxv2f16_poison(half %h, i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv2f16_poison:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z1.d, #0, #1
+; CHECK-NEXT: mov z2.d, x0
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpeq p0.d, p0/z, z1.d, z2.d
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 2 x half> poison, half %h, i64 %idx
+ ret <vscale x 2 x half> %res
+}
+
+define <vscale x 2 x half> @test_lanex_nxv2f16_poison_imm(i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv2f16_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.d, #0, #1
+; CHECK-NEXT: mov z1.d, x0
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: fmov h0, #1.50000000
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 2 x half> poison, half 1.5, i64 %idx
+ ret <vscale x 2 x half> %res
+}
+
+define <vscale x 4 x half> @test_lanex_nxv4f16_poison(half %h, i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv4f16_poison:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z1.s, #0, #1
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z1.s, z2.s
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 4 x half> poison, half %h, i64 %idx
+ ret <vscale x 4 x half> %res
+}
+
+define <vscale x 4 x half> @test_lanex_nxv4f16_poison_imm(i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv4f16_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.s, #0, #1
+; CHECK-NEXT: mov z1.s, w0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: fmov h0, #1.50000000
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 4 x half> poison, half 1.5, i64 %idx
+ ret <vscale x 4 x half> %res
+}
+
+define <vscale x 8 x half> @test_lanex_nxv8f16_poison(half %h, i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv8f16_poison:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z1.h, #0, #1
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 8 x half> poison, half %h, i64 %idx
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 8 x half> @test_lanex_nxv8f16_poison_imm(i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv8f16_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.h, #0, #1
+; CHECK-NEXT: mov z1.h, w0
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: fmov h0, #1.50000000
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 8 x half> poison, half 1.5, i64 %idx
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 2 x bfloat> @test_lanex_nxv2bf16_poison(bfloat %h, i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv2bf16_poison:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z1.d, #0, #1
+; CHECK-NEXT: mov z2.d, x0
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpeq p0.d, p0/z, z1.d, z2.d
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 2 x bfloat> poison, bfloat %h, i64 %idx
+ ret <vscale x 2 x bfloat> %res
+}
+
+define <vscale x 2 x bfloat> @test_lanex_nxv2bf16_poison_imm(i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv2bf16_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.d, #0, #1
+; CHECK-NEXT: mov z1.d, x0
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: fmov h0, #1.93750000
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 2 x bfloat> poison, bfloat 1.5, i64 %idx
+ ret <vscale x 2 x bfloat> %res
+}
+
+define <vscale x 4 x bfloat> @test_lanex_nxv4bf16_poison(bfloat %h, i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv4bf16_poison:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z1.s, #0, #1
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z1.s, z2.s
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 4 x bfloat> poison, bfloat %h, i64 %idx
+ ret <vscale x 4 x bfloat> %res
+}
+
+define <vscale x 4 x bfloat> @test_lanex_nxv4bf16_poison_imm(i64 %idx) {
+; CHECK-LABEL: test_lanex_nxv4bf16_poison_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: index z0.s, #0, #1
+; CHECK-NEXT: mov z1.s, w0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: fmov h0, #1.93750000
+; CHECK-NEXT: mov z0.h, p0/m, h0
+; CHECK-NEXT: ret
+ %res = insertelement <vscale x 4 x bfloat> poison, bfloat 1.5, i64 %idx
+ ret <vscale x 4 x bfloat> %res
+}
+
+define <vscale x 8 x bfloat> @test_lanex_nxv8bf16_poison(bfloat %h, i64 %idx) {
----------------
paulwalker-arm wrote:
Why do you need DAG->DAG tests? The point of unit tests is to ensure every line of new code is tested. https://github.com/llvm/llvm-project/pull/173005 is effectively a two line DAG combine that looks easily testable with a few llc tests (zero index, var index, undef invec, non-undef invective) some of which might already exist.
As the combine does not care about the vector or element types (other than to require a scalable vector), there is nothing in that domain to test?
https://github.com/llvm/llvm-project/pull/173003
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