[llvm] [MIRVRegNamerUtils] Handle instructions with multiple definitions (PR #172982)

[Juan Manuel Martinez Caamaño via llvm-commits]

================
@@ -0,0 +1,37 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: multi_def_renaming
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $vgpr3
+    ; CHECK-LABEL: name: multi_def_renaming
+    ; CHECK: liveins: $sgpr0_sgpr1, $vgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %bb0_1062d9001ab55240__1:vgpr_32 = COPY $vgpr3
+    ; CHECK-NEXT: %bb0_d404709a296ee532__1:sreg_32 = COPY $sgpr1
+    ; CHECK-NEXT: %bb0_bbc0cd19274e6c7b__1:sreg_32 = COPY $sgpr0
+    ; CHECK-NEXT: %bb0_0a0c5272a7d346ac__1:vgpr_32 = V_ADD_U32_e64 %bb0_1062d9001ab55240__1, %bb0_1062d9001ab55240__1, 0, implicit $exec
+    ; CHECK-NEXT: %bb0_079c949829e5b8ca__1:vgpr_32 = V_SUB_U32_e64 %bb0_0a0c5272a7d346ac__1, 2, 0, implicit $exec
+    ; CHECK-NEXT: %bb0_2480fd234d71ac02__1:sreg_64 = REG_SEQUENCE %bb0_bbc0cd19274e6c7b__1, %subreg.sub0, %bb0_d404709a296ee532__1, %subreg.sub1
+    ; CHECK-NEXT: %bb0_3e89a8fc566e3506__1:vreg_64 = REG_SEQUENCE %bb0_0a0c5272a7d346ac__1, %subreg.sub0, %bb0_0a0c5272a7d346ac__1, %subreg.sub1
+    ; CHECK-NEXT: %bb0_af82b3d077ca950c__1:vreg_64, %bb0_af82b3d077ca950c__2:sreg_64 = V_MAD_U64_U32_e64 %bb0_0a0c5272a7d346ac__1, %bb0_0a0c5272a7d346ac__1, %bb0_3e89a8fc566e3506__1, 0, implicit $exec
+    ; CHECK-NEXT: %bb0_640fe5cc4c57ace5__1:vgpr_32 = COPY %bb0_af82b3d077ca950c__2.sub0
+    ; CHECK-NEXT: S_ENDPGM 0
+    %0:sreg_32 = COPY $sgpr0
+    %1:sreg_32 = COPY $sgpr1
+    %2:vgpr_32 = COPY $vgpr3
+    %3:vgpr_32 = V_ADD_U32_e64 %2, %2, 0, implicit $exec
+    %4:vgpr_32 = V_SUB_U32_e64 %3, 2, 0, implicit $exec
+    %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %3, %subreg.sub1
+    %6:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
+    %7:vreg_64, %8:sreg_64 = V_MAD_U64_U32_e64 %3,  %3, %5, 0, implicit $exec
----------------
jmmartinez wrote:

Can you simplify the test? The only relevant instruction for the proposed change is `V_MAD_U64_U32_e64`.

I was thinking about using live-in phys-regs for the inputs of the instruction:

```asm
    liveins: $vgpr3, $vgpr4_vgpr5
    %0:vreg_64, %1:sreg_64 = V_MAD_U64_U32_e64 $vgpr3, $vgpr3, $vgpr4_vgpr5, 0, implicit $exec
    %2:vgpr_32 = COPY %1.sub0
    S_ENDPGM 0
```

https://github.com/llvm/llvm-project/pull/172982