[llvm] [AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (PR #170335)

[Matt Arsenault via llvm-commits]

================
@@ -102,6 +102,34 @@ struct GCNRegPressure {
                                                 DynamicVGPRBlockSize));
   }
 
+  unsigned getVGPRSpills(MachineFunction &MF) {
+    const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+    if (!ST.hasGFX90AInsts())
+      return 0;
+
+    std::pair<unsigned, unsigned> MaxVectorRegs =
+        ST.getMaxNumVectorRegs(MF.getFunction());
----------------
arsenm wrote:

It looks like this function is going to be called many times. These getters for the number of registers (getMaxNumVectorRegs and getMaxNumVGPRs) are not actually trivial, and doing a bunch of attribute string parsing. These should be computed once (or you should be able to take the value directly from RegisterClassInfo) 

https://github.com/llvm/llvm-project/pull/170335