[llvm] [AArch64] Fix assertion failure during promotion of EXTEND_VECTOR_INREG. (PR #171619)

[Matt Arsenault via llvm-commits]

================
@@ -6206,6 +6206,15 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
       default:
         llvm_unreachable("Node has unexpected Opcode");
     }
+    unsigned NewSize = NVT.getSizeInBits();
+    if (Promoted.getValueType().getSizeInBits() > NewSize) {
+      EVT ExtractVT = EVT::getVectorVT(
+          *DAG.getContext(), Promoted.getValueType().getScalarType(),
+          NewSize / Promoted.getScalarValueSizeInBits());
----------------
arsenm wrote:

```suggestion
      EVT ExtractVT = EVT::getVectorVT(
          *DAG.getContext(), Promoted.getValueType().getVectorElementType(),
          VT.getVectorElementCount());
```

https://github.com/llvm/llvm-project/pull/171619