[llvm] [AMDGPU] Allow allocation of lo128 registers from all banks (PR #172614)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> A straight forward solution would be to create a register class
with all registers having bit 8 of the encoding zero, i.e. to
create a register class with holes punched in it: [0-127, 256-383,
512-639, 768-895]. LLVM, however, does not like register classes
with punched holes when they also have subregisters. The cross-
product of all classes explodes and some combinations of a 'class
having a common subreg with another' becomeing impossible. Just
doing so explodes our register info to 4+Gb, uncompilable too.

I don't understand the problem here. Fix the tablegen bug? It would be far nicer to express this as a class instead of functionally creating a class that requires special casing 

https://github.com/llvm/llvm-project/pull/172614