[llvm] [AArch64] Initial Olympus scheduling model. (PR #171607)
Ricardo Jesus via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 18 08:41:09 PST 2025
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@@ -0,0 +1,3377 @@
+//=- AArch64SchedOlympus.td - Olympus Scheduling Defs --------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the scheduling model for the NVIDIA Olympus processors.
+// All information is taken from the Olympus Software Optimisation guide:
+//
+// https://docs.nvidia.com/olympus-cpu-core-software-optimization-guide-dp12531-001v0-7.pdf
+//
+//===----------------------------------------------------------------------===//
+
+def OlympusModel : SchedMachineModel {
+ // NOTE: Unless otherwise stated, values unspecified in the Olympus SWOG are
+ // copied from the Neoverse V2 model.
+ let IssueWidth = 10; // Maximum macro-ops dispatched per cycle.
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasCPA, HasCSSC,
+ HasMatMulFP64]);
+}
+
+//===----------------------------------------------------------------------===//
+// In the Olympus core, instructions are first fetched and decoded into
----------------
rj-jesus wrote:
Yeah, I thought the bit describing how MOps are fetched, decoded, and may later be split could be useful, but I don't have strong feelings about it. It is paraphrasing the SWOG. I left it as is for now, but if you'd rather I remove this just let me know.
https://github.com/llvm/llvm-project/pull/171607
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