[llvm] [X86] combineConcatVectorOps - add handling for CVTPS2DQ/CVTTPS2DQ vector ops (PR #172841)
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Thu Dec 18 04:18:39 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/172841.diff
3 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+16)
- (modified) llvm/test/CodeGen/X86/combine-cvtp2si.ll (+11-12)
- (modified) llvm/test/CodeGen/X86/combine-cvttp2si.ll (+11-12)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index fd72f0815876f..dc25873bfc8e9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -59730,6 +59730,22 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
Op0.getOperand(1));
}
break;
+ case X86ISD::CVTP2SI:
+ case X86ISD::CVTTP2SI:
+ if (!IsSplat &&
+ (VT.is256BitVector() ||
+ (VT.is512BitVector() && Subtarget.useAVX512Regs())) &&
+ llvm::all_of(Ops, [VT](SDValue Op) {
+ return Op.getOperand(0).getScalarValueSizeInBits() ==
+ VT.getScalarSizeInBits();
+ })) {
+ // TODO: Add handling for different sized src/dst elements.
+ EVT SrcVT = Op0.getOperand(0).getValueType();
+ EVT NewSrcVT = EVT::getVectorVT(Ctx, SrcVT.getScalarType(),
+ NumOps * SrcVT.getVectorNumElements());
+ return DAG.getNode(Opcode, DL, VT, ConcatSubOperand(NewSrcVT, Ops, 0));
+ }
+ break;
case X86ISD::HADD:
case X86ISD::HSUB:
case X86ISD::FHADD:
diff --git a/llvm/test/CodeGen/X86/combine-cvtp2si.ll b/llvm/test/CodeGen/X86/combine-cvtp2si.ll
index 838271b70683b..033c752a9734b 100644
--- a/llvm/test/CodeGen/X86/combine-cvtp2si.ll
+++ b/llvm/test/CodeGen/X86/combine-cvtp2si.ll
@@ -6,9 +6,9 @@
define <8 x i32> @concat_cvtps2dq_v8i32_v4f32(<4 x float> %a0, <4 x float> %a1) {
; AVX-LABEL: concat_cvtps2dq_v8i32_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vcvtps2dq %xmm0, %xmm0
-; AVX-NEXT: vcvtps2dq %xmm1, %xmm1
+; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT: vcvtps2dq %ymm0, %ymm0
; AVX-NEXT: retq
%v0 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0)
%v1 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a1)
@@ -19,23 +19,22 @@ define <8 x i32> @concat_cvtps2dq_v8i32_v4f32(<4 x float> %a0, <4 x float> %a1)
define <16 x i32> @concat_cvtps2dq_v16i32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {
; AVX1OR2-LABEL: concat_cvtps2dq_v16i32_v4f32:
; AVX1OR2: # %bb.0:
-; AVX1OR2-NEXT: vcvtps2dq %xmm0, %xmm0
-; AVX1OR2-NEXT: vcvtps2dq %xmm1, %xmm1
-; AVX1OR2-NEXT: vcvtps2dq %xmm2, %xmm2
-; AVX1OR2-NEXT: vcvtps2dq %xmm3, %xmm3
+; AVX1OR2-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm2
+; AVX1OR2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1OR2-NEXT: vcvtps2dq %ymm0, %ymm0
; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1
+; AVX1OR2-NEXT: vcvtps2dq %ymm1, %ymm1
; AVX1OR2-NEXT: retq
;
; AVX512-LABEL: concat_cvtps2dq_v16i32_v4f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vcvtps2dq %xmm0, %xmm0
-; AVX512-NEXT: vcvtps2dq %xmm1, %xmm1
-; AVX512-NEXT: vcvtps2dq %xmm2, %xmm2
-; AVX512-NEXT: vcvtps2dq %xmm3, %xmm3
+; AVX512-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm2
+; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX512-NEXT: vcvtps2dq %zmm0, %zmm0
; AVX512-NEXT: retq
%v0 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0)
%v1 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a1)
@@ -56,9 +55,9 @@ define <16 x i32> @concat_cvtps2dq_v16i32_v8f32(<8 x float> %a0, <8 x float> %a1
;
; AVX512-LABEL: concat_cvtps2dq_v16i32_v8f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vcvtps2dq %ymm0, %ymm0
-; AVX512-NEXT: vcvtps2dq %ymm1, %ymm1
+; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX512-NEXT: vcvtps2dq %zmm0, %zmm0
; AVX512-NEXT: retq
%v0 = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0)
%v1 = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a1)
diff --git a/llvm/test/CodeGen/X86/combine-cvttp2si.ll b/llvm/test/CodeGen/X86/combine-cvttp2si.ll
index caa3f5eedbb14..2fa402a9e90e3 100644
--- a/llvm/test/CodeGen/X86/combine-cvttp2si.ll
+++ b/llvm/test/CodeGen/X86/combine-cvttp2si.ll
@@ -6,9 +6,9 @@
define <8 x i32> @concat_cvttps2dq_v8i32_v4f32(<4 x float> %a0, <4 x float> %a1) {
; AVX-LABEL: concat_cvttps2dq_v8i32_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vcvttps2dq %xmm0, %xmm0
-; AVX-NEXT: vcvttps2dq %xmm1, %xmm1
+; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX-NEXT: retq
%v0 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0)
%v1 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a1)
@@ -19,23 +19,22 @@ define <8 x i32> @concat_cvttps2dq_v8i32_v4f32(<4 x float> %a0, <4 x float> %a1)
define <16 x i32> @concat_cvttps2dq_v16i32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {
; AVX1OR2-LABEL: concat_cvttps2dq_v16i32_v4f32:
; AVX1OR2: # %bb.0:
-; AVX1OR2-NEXT: vcvttps2dq %xmm0, %xmm0
-; AVX1OR2-NEXT: vcvttps2dq %xmm1, %xmm1
-; AVX1OR2-NEXT: vcvttps2dq %xmm2, %xmm2
-; AVX1OR2-NEXT: vcvttps2dq %xmm3, %xmm3
+; AVX1OR2-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm2
+; AVX1OR2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1OR2-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1
+; AVX1OR2-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX1OR2-NEXT: retq
;
; AVX512-LABEL: concat_cvttps2dq_v16i32_v4f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vcvttps2dq %xmm0, %xmm0
-; AVX512-NEXT: vcvttps2dq %xmm1, %xmm1
-; AVX512-NEXT: vcvttps2dq %xmm2, %xmm2
-; AVX512-NEXT: vcvttps2dq %xmm3, %xmm3
+; AVX512-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm2
+; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0
; AVX512-NEXT: retq
%v0 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0)
%v1 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a1)
@@ -56,9 +55,9 @@ define <16 x i32> @concat_cvttps2dq_v16i32_v8f32(<8 x float> %a0, <8 x float> %a
;
; AVX512-LABEL: concat_cvttps2dq_v16i32_v8f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX512-NEXT: vcvttps2dq %ymm1, %ymm1
+; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0
; AVX512-NEXT: retq
%v0 = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)
%v1 = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a1)
``````````
</details>
https://github.com/llvm/llvm-project/pull/172841
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