[llvm] [AArch64] Initial Olympus scheduling model. (PR #171607)

[Sjoerd Meijer via llvm-commits]

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@@ -2089,7 +2089,7 @@ class SpecialReturn<bits<4> opc, string asm>
 let mayLoad = 1 in
 class RCPCLoad<bits<2> sz, string asm, RegisterClass RC>
   : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>,
-  Sched<[]> {
+  Sched<[WriteLD]> {
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sjoerdmeijer wrote:

Same sort of question: this is a fix that could be separate patch? Probably fine to fix it up here...

https://github.com/llvm/llvm-project/pull/171607