[llvm] [AArch64] Add scal_to_vec patterns for SIMD convert intrinsics (PR #172837)
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Thu Dec 18 03:19:54 PST 2025
https://github.com/Lukacma created https://github.com/llvm/llvm-project/pull/172837
This patch adds patterns for lowering FCVT intrinsics followed by scalar_to_vector node into SIMD FCVT instructions. This is done to prevent extra moves from being generated when GPR version would be used.
>From f453fd3056b9ffbdf377bc4b5607ef3569049b8b Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Thu, 18 Dec 2025 11:16:41 +0000
Subject: [PATCH] [AArch64] Add scal_to_vec patterns for SIMD convert
intrinsics
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 17 +-
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 170 ++
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.s | 1515 +++++++++++++++++
.../AArch64/arm64-cvt-simd-intrinsics.ll | 334 +++-
...arm64-fixed-point-scalar-cvt-dagcombine.ll | 3 +-
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 57 +-
llvm/test/CodeGen/AArch64/arm64-vcvt.ll | 28 +-
.../CodeGen/AArch64/fp-intrinsics-vector.ll | 6 +-
.../AArch64/sve-fixed-length-fp-to-int.ll | 6 +-
9 files changed, 2064 insertions(+), 72 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.s
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index c22929f379dfc..447fd9ef66343 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -6563,12 +6563,19 @@ multiclass FPToIntegerSIMDScalarPatterns<SDPatternOperator OpN, string INST> {
(!cast<Instruction>(INST # DHr) FPR16:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (OpN (f32 FPR32:$Rn))))),
(!cast<Instruction>(INST # DSr) FPR32:$Rn)>;
+
+ def : Pat<(v1i64 (scalar_to_vector (i64 (OpN (f16 FPR16:$Rn))))),
+ (!cast<Instruction>(INST # DHr) FPR16:$Rn)>;
+ def : Pat<(v1i64 (scalar_to_vector (i64 (OpN (f32 FPR32:$Rn))))),
+ (!cast<Instruction>(INST # DSr) FPR32:$Rn)>;
}
def : Pat<(f32 (bitconvert (i32 (OpN (f32 FPR32:$Rn))))),
(!cast<Instruction>(INST # v1i32) FPR32:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (OpN (f64 FPR64:$Rn))))),
(!cast<Instruction>(INST # v1i64) FPR64:$Rn)>;
-
+
+ def : Pat<(v1i64 (scalar_to_vector (i64 (OpN (f64 FPR64:$Rn))))),
+ (!cast<Instruction>(INST # v1i64) FPR64:$Rn)>;
}
defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtas, "FCVTAS">;
defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtau, "FCVTAU">;
@@ -6611,12 +6618,20 @@ multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
(!cast<Instruction>(INST # DSr) $Rn)>;
def : Pat<(f32 (bitconvert (i32 (round f64:$Rn)))),
(!cast<Instruction>(INST # SDr) $Rn)>;
+
+ def : Pat<(v1i64 (scalar_to_vector (i64 (round f16:$Rn)))),
+ (!cast<Instruction>(INST # DHr) $Rn)>;
+ def : Pat<(v1i64 (scalar_to_vector (i64 (round f32:$Rn)))),
+ (!cast<Instruction>(INST # DSr) $Rn)>;
}
def : Pat<(f32 (bitconvert (i32 (round f32:$Rn)))),
(!cast<Instruction>(INST # v1i32) $Rn)>;
def : Pat<(f64 (bitconvert (i64 (round f64:$Rn)))),
(!cast<Instruction>(INST # v1i64) $Rn)>;
+ def : Pat<(v1i64 (scalar_to_vector (i64 (round f64:$Rn)))),
+ (!cast<Instruction>(INST # v1i64) $Rn)>;
+
let Predicates = [HasFullFP16] in {
def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index a729772f2897a..ebaca00d2cdb9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -15,6 +15,10 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f32_simd
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtzs_scalar_to_vector_h_strict
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtzs_scalar_to_vector_s_strict
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtzu_scalar_to_vector_h_strict
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtzu_scalar_to_vector_s_strict
;
; FPTOI
@@ -1941,3 +1945,169 @@ define double @fcvtzu_dd_simd(double %a) {
%bc = bitcast i64 %i to double
ret double %bc
}
+
+;
+; FPTOI scalar_to_vector
+;
+
+define <1 x i64> @fcvtzs_scalar_to_vector_h(half %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_scalar_to_vector_h:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzs_scalar_to_vector_h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, h0
+; CHECK-NEXT: ret
+ %val = fptosi half %a to i64
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzs_scalar_to_vector_s(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_scalar_to_vector_s:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzs_scalar_to_vector_s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, s0
+; CHECK-NEXT: ret
+ %val = fptosi float %a to i64
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzs_scalar_to_vector_d(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_scalar_to_vector_d:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzs_scalar_to_vector_d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, d0
+; CHECK-NEXT: ret
+ %val = fptosi double %a to i64
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzu_scalar_to_vector_h(half %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_scalar_to_vector_h:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzu_scalar_to_vector_h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, h0
+; CHECK-NEXT: ret
+ %val = fptoui half %a to i64
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzu_scalar_to_vector_s(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_scalar_to_vector_s:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzu_scalar_to_vector_s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, s0
+; CHECK-NEXT: ret
+ %val = fptoui float %a to i64
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzu_scalar_to_vector_d(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_scalar_to_vector_d:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzu_scalar_to_vector_d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, d0
+; CHECK-NEXT: ret
+ %val = fptoui double %a to i64
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+;
+; FPTOI scalar_to_vector strictfp
+;
+
+define <1 x i64> @fcvtzs_scalar_to_vector_h_strict(half %x) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_scalar_to_vector_h_strict:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzs_scalar_to_vector_h_strict:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, h0
+; CHECK-NEXT: ret
+ %val = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %x, metadata !"fpexcept.strict")
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzs_scalar_to_vector_s_strict(float %x) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_scalar_to_vector_s_strict:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzs_scalar_to_vector_s_strict:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, s0
+; CHECK-NEXT: ret
+ %val = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %x, metadata !"fpexcept.strict")
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzu_scalar_to_vector_h_strict(half %x) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_scalar_to_vector_h_strict:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzu_scalar_to_vector_h_strict:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, h0
+; CHECK-NEXT: ret
+ %val = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %x, metadata !"fpexcept.strict")
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzu_scalar_to_vector_s_strict(float %x) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_scalar_to_vector_s_strict:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
+; CHECK-NOFPRCVT-NEXT: fmov d0, x8
+; CHECK-NOFPRCVT-NEXT: ret
+;
+; CHECK-LABEL: fcvtzu_scalar_to_vector_s_strict:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, s0
+; CHECK-NEXT: ret
+ %val = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %x, metadata !"fpexcept.strict")
+ %vec = insertelement <1 x i64> poison, i64 %val, i32 0
+ ret <1 x i64> %vec
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.s b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.s
new file mode 100644
index 0000000000000..0850b306e8c79
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.s
@@ -0,0 +1,1515 @@
+ .file "arm64-cvt-simd-fptoi.ll"
+ .text
+ .globl test_fptosi_f16_i32_simd // -- Begin function test_fptosi_f16_i32_simd
+ .p2align 2
+ .type test_fptosi_f16_i32_simd, at function
+test_fptosi_f16_i32_simd: // @test_fptosi_f16_i32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, h0
+ ret
+.Lfunc_end0:
+ .size test_fptosi_f16_i32_simd, .Lfunc_end0-test_fptosi_f16_i32_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptosi_f16_i64_simd // -- Begin function test_fptosi_f16_i64_simd
+ .p2align 2
+ .type test_fptosi_f16_i64_simd, at function
+test_fptosi_f16_i64_simd: // @test_fptosi_f16_i64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, h0
+ ret
+.Lfunc_end1:
+ .size test_fptosi_f16_i64_simd, .Lfunc_end1-test_fptosi_f16_i64_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptosi_f64_i32_simd // -- Begin function test_fptosi_f64_i32_simd
+ .p2align 2
+ .type test_fptosi_f64_i32_simd, at function
+test_fptosi_f64_i32_simd: // @test_fptosi_f64_i32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, d0
+ ret
+.Lfunc_end2:
+ .size test_fptosi_f64_i32_simd, .Lfunc_end2-test_fptosi_f64_i32_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptosi_f32_i64_simd // -- Begin function test_fptosi_f32_i64_simd
+ .p2align 2
+ .type test_fptosi_f32_i64_simd, at function
+test_fptosi_f32_i64_simd: // @test_fptosi_f32_i64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, s0
+ ret
+.Lfunc_end3:
+ .size test_fptosi_f32_i64_simd, .Lfunc_end3-test_fptosi_f32_i64_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptosi_f64_i64_simd // -- Begin function test_fptosi_f64_i64_simd
+ .p2align 2
+ .type test_fptosi_f64_i64_simd, at function
+test_fptosi_f64_i64_simd: // @test_fptosi_f64_i64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end4:
+ .size test_fptosi_f64_i64_simd, .Lfunc_end4-test_fptosi_f64_i64_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptosi_f32_i32_simd // -- Begin function test_fptosi_f32_i32_simd
+ .p2align 2
+ .type test_fptosi_f32_i32_simd, at function
+test_fptosi_f32_i32_simd: // @test_fptosi_f32_i32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, s0
+ ret
+.Lfunc_end5:
+ .size test_fptosi_f32_i32_simd, .Lfunc_end5-test_fptosi_f32_i32_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptoui_f16_i32_simd // -- Begin function test_fptoui_f16_i32_simd
+ .p2align 2
+ .type test_fptoui_f16_i32_simd, at function
+test_fptoui_f16_i32_simd: // @test_fptoui_f16_i32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, h0
+ ret
+.Lfunc_end6:
+ .size test_fptoui_f16_i32_simd, .Lfunc_end6-test_fptoui_f16_i32_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptoui_f16_i64_simd // -- Begin function test_fptoui_f16_i64_simd
+ .p2align 2
+ .type test_fptoui_f16_i64_simd, at function
+test_fptoui_f16_i64_simd: // @test_fptoui_f16_i64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, h0
+ ret
+.Lfunc_end7:
+ .size test_fptoui_f16_i64_simd, .Lfunc_end7-test_fptoui_f16_i64_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptoui_f64_i32_simd // -- Begin function test_fptoui_f64_i32_simd
+ .p2align 2
+ .type test_fptoui_f64_i32_simd, at function
+test_fptoui_f64_i32_simd: // @test_fptoui_f64_i32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, d0
+ ret
+.Lfunc_end8:
+ .size test_fptoui_f64_i32_simd, .Lfunc_end8-test_fptoui_f64_i32_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptoui_f32_i64_simd // -- Begin function test_fptoui_f32_i64_simd
+ .p2align 2
+ .type test_fptoui_f32_i64_simd, at function
+test_fptoui_f32_i64_simd: // @test_fptoui_f32_i64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, s0
+ ret
+.Lfunc_end9:
+ .size test_fptoui_f32_i64_simd, .Lfunc_end9-test_fptoui_f32_i64_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptoui_f64_i64_simd // -- Begin function test_fptoui_f64_i64_simd
+ .p2align 2
+ .type test_fptoui_f64_i64_simd, at function
+test_fptoui_f64_i64_simd: // @test_fptoui_f64_i64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, d0
+ ret
+.Lfunc_end10:
+ .size test_fptoui_f64_i64_simd, .Lfunc_end10-test_fptoui_f64_i64_simd
+ .cfi_endproc
+ // -- End function
+ .globl test_fptoui_f32_i32_simd // -- Begin function test_fptoui_f32_i32_simd
+ .p2align 2
+ .type test_fptoui_f32_i32_simd, at function
+test_fptoui_f32_i32_simd: // @test_fptoui_f32_i32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, s0
+ ret
+.Lfunc_end11:
+ .size test_fptoui_f32_i32_simd, .Lfunc_end11-test_fptoui_f32_i32_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptosi_i32_f16_simd // -- Begin function fptosi_i32_f16_simd
+ .p2align 2
+ .type fptosi_i32_f16_simd, at function
+fptosi_i32_f16_simd: // @fptosi_i32_f16_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, h0
+ ret
+.Lfunc_end12:
+ .size fptosi_i32_f16_simd, .Lfunc_end12-fptosi_i32_f16_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptosi_i64_f16_simd // -- Begin function fptosi_i64_f16_simd
+ .p2align 2
+ .type fptosi_i64_f16_simd, at function
+fptosi_i64_f16_simd: // @fptosi_i64_f16_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, h0
+ ret
+.Lfunc_end13:
+ .size fptosi_i64_f16_simd, .Lfunc_end13-fptosi_i64_f16_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptosi_i64_f32_simd // -- Begin function fptosi_i64_f32_simd
+ .p2align 2
+ .type fptosi_i64_f32_simd, at function
+fptosi_i64_f32_simd: // @fptosi_i64_f32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, s0
+ ret
+.Lfunc_end14:
+ .size fptosi_i64_f32_simd, .Lfunc_end14-fptosi_i64_f32_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptosi_i32_f64_simd // -- Begin function fptosi_i32_f64_simd
+ .p2align 2
+ .type fptosi_i32_f64_simd, at function
+fptosi_i32_f64_simd: // @fptosi_i32_f64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, d0
+ ret
+.Lfunc_end15:
+ .size fptosi_i32_f64_simd, .Lfunc_end15-fptosi_i32_f64_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptosi_i64_f64_simd // -- Begin function fptosi_i64_f64_simd
+ .p2align 2
+ .type fptosi_i64_f64_simd, at function
+fptosi_i64_f64_simd: // @fptosi_i64_f64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end16:
+ .size fptosi_i64_f64_simd, .Lfunc_end16-fptosi_i64_f64_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptosi_i32_f32_simd // -- Begin function fptosi_i32_f32_simd
+ .p2align 2
+ .type fptosi_i32_f32_simd, at function
+fptosi_i32_f32_simd: // @fptosi_i32_f32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, s0
+ ret
+.Lfunc_end17:
+ .size fptosi_i32_f32_simd, .Lfunc_end17-fptosi_i32_f32_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptoui_i32_f16_simd // -- Begin function fptoui_i32_f16_simd
+ .p2align 2
+ .type fptoui_i32_f16_simd, at function
+fptoui_i32_f16_simd: // @fptoui_i32_f16_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, h0
+ ret
+.Lfunc_end18:
+ .size fptoui_i32_f16_simd, .Lfunc_end18-fptoui_i32_f16_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptoui_i64_f16_simd // -- Begin function fptoui_i64_f16_simd
+ .p2align 2
+ .type fptoui_i64_f16_simd, at function
+fptoui_i64_f16_simd: // @fptoui_i64_f16_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, h0
+ ret
+.Lfunc_end19:
+ .size fptoui_i64_f16_simd, .Lfunc_end19-fptoui_i64_f16_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptoui_i64_f32_simd // -- Begin function fptoui_i64_f32_simd
+ .p2align 2
+ .type fptoui_i64_f32_simd, at function
+fptoui_i64_f32_simd: // @fptoui_i64_f32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, s0
+ ret
+.Lfunc_end20:
+ .size fptoui_i64_f32_simd, .Lfunc_end20-fptoui_i64_f32_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptoui_i32_f64_simd // -- Begin function fptoui_i32_f64_simd
+ .p2align 2
+ .type fptoui_i32_f64_simd, at function
+fptoui_i32_f64_simd: // @fptoui_i32_f64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, d0
+ ret
+.Lfunc_end21:
+ .size fptoui_i32_f64_simd, .Lfunc_end21-fptoui_i32_f64_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptoui_i64_f64_simd // -- Begin function fptoui_i64_f64_simd
+ .p2align 2
+ .type fptoui_i64_f64_simd, at function
+fptoui_i64_f64_simd: // @fptoui_i64_f64_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, d0
+ ret
+.Lfunc_end22:
+ .size fptoui_i64_f64_simd, .Lfunc_end22-fptoui_i64_f64_simd
+ .cfi_endproc
+ // -- End function
+ .globl fptoui_i32_f32_simd // -- Begin function fptoui_i32_f32_simd
+ .p2align 2
+ .type fptoui_i32_f32_simd, at function
+fptoui_i32_f32_simd: // @fptoui_i32_f32_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, s0
+ ret
+.Lfunc_end23:
+ .size fptoui_i32_f32_simd, .Lfunc_end23-fptoui_i32_f32_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_ds_round_simd // -- Begin function fcvtas_ds_round_simd
+ .p2align 2
+ .type fcvtas_ds_round_simd, at function
+fcvtas_ds_round_simd: // @fcvtas_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas d0, s0
+ ret
+.Lfunc_end24:
+ .size fcvtas_ds_round_simd, .Lfunc_end24-fcvtas_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_sd_round_simd // -- Begin function fcvtas_sd_round_simd
+ .p2align 2
+ .type fcvtas_sd_round_simd, at function
+fcvtas_sd_round_simd: // @fcvtas_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas s0, d0
+ ret
+.Lfunc_end25:
+ .size fcvtas_sd_round_simd, .Lfunc_end25-fcvtas_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_ss_round_simd // -- Begin function fcvtas_ss_round_simd
+ .p2align 2
+ .type fcvtas_ss_round_simd, at function
+fcvtas_ss_round_simd: // @fcvtas_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas s0, s0
+ ret
+.Lfunc_end26:
+ .size fcvtas_ss_round_simd, .Lfunc_end26-fcvtas_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_dd_round_simd // -- Begin function fcvtas_dd_round_simd
+ .p2align 2
+ .type fcvtas_dd_round_simd, at function
+fcvtas_dd_round_simd: // @fcvtas_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas d0, d0
+ ret
+.Lfunc_end27:
+ .size fcvtas_dd_round_simd, .Lfunc_end27-fcvtas_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_ds_round_simd // -- Begin function fcvtau_ds_round_simd
+ .p2align 2
+ .type fcvtau_ds_round_simd, at function
+fcvtau_ds_round_simd: // @fcvtau_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtau d0, s0
+ ret
+.Lfunc_end28:
+ .size fcvtau_ds_round_simd, .Lfunc_end28-fcvtau_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_sd_round_simd // -- Begin function fcvtau_sd_round_simd
+ .p2align 2
+ .type fcvtau_sd_round_simd, at function
+fcvtau_sd_round_simd: // @fcvtau_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtau s0, d0
+ ret
+.Lfunc_end29:
+ .size fcvtau_sd_round_simd, .Lfunc_end29-fcvtau_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_ss_round_simd // -- Begin function fcvtau_ss_round_simd
+ .p2align 2
+ .type fcvtau_ss_round_simd, at function
+fcvtau_ss_round_simd: // @fcvtau_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas s0, s0
+ ret
+.Lfunc_end30:
+ .size fcvtau_ss_round_simd, .Lfunc_end30-fcvtau_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_dd_round_simd // -- Begin function fcvtau_dd_round_simd
+ .p2align 2
+ .type fcvtau_dd_round_simd, at function
+fcvtau_dd_round_simd: // @fcvtau_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas d0, d0
+ ret
+.Lfunc_end31:
+ .size fcvtau_dd_round_simd, .Lfunc_end31-fcvtau_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_ds_round_simd // -- Begin function fcvtms_ds_round_simd
+ .p2align 2
+ .type fcvtms_ds_round_simd, at function
+fcvtms_ds_round_simd: // @fcvtms_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms d0, s0
+ ret
+.Lfunc_end32:
+ .size fcvtms_ds_round_simd, .Lfunc_end32-fcvtms_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_sd_round_simd // -- Begin function fcvtms_sd_round_simd
+ .p2align 2
+ .type fcvtms_sd_round_simd, at function
+fcvtms_sd_round_simd: // @fcvtms_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms s0, d0
+ ret
+.Lfunc_end33:
+ .size fcvtms_sd_round_simd, .Lfunc_end33-fcvtms_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_ss_round_simd // -- Begin function fcvtms_ss_round_simd
+ .p2align 2
+ .type fcvtms_ss_round_simd, at function
+fcvtms_ss_round_simd: // @fcvtms_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms s0, s0
+ ret
+.Lfunc_end34:
+ .size fcvtms_ss_round_simd, .Lfunc_end34-fcvtms_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_dd_round_simd // -- Begin function fcvtms_dd_round_simd
+ .p2align 2
+ .type fcvtms_dd_round_simd, at function
+fcvtms_dd_round_simd: // @fcvtms_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms d0, d0
+ ret
+.Lfunc_end35:
+ .size fcvtms_dd_round_simd, .Lfunc_end35-fcvtms_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_ds_round_simd // -- Begin function fcvtmu_ds_round_simd
+ .p2align 2
+ .type fcvtmu_ds_round_simd, at function
+fcvtmu_ds_round_simd: // @fcvtmu_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtmu d0, s0
+ ret
+.Lfunc_end36:
+ .size fcvtmu_ds_round_simd, .Lfunc_end36-fcvtmu_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_sd_round_simd // -- Begin function fcvtmu_sd_round_simd
+ .p2align 2
+ .type fcvtmu_sd_round_simd, at function
+fcvtmu_sd_round_simd: // @fcvtmu_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtmu s0, d0
+ ret
+.Lfunc_end37:
+ .size fcvtmu_sd_round_simd, .Lfunc_end37-fcvtmu_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_ss_round_simd // -- Begin function fcvtmu_ss_round_simd
+ .p2align 2
+ .type fcvtmu_ss_round_simd, at function
+fcvtmu_ss_round_simd: // @fcvtmu_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms s0, s0
+ ret
+.Lfunc_end38:
+ .size fcvtmu_ss_round_simd, .Lfunc_end38-fcvtmu_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_dd_round_simd // -- Begin function fcvtmu_dd_round_simd
+ .p2align 2
+ .type fcvtmu_dd_round_simd, at function
+fcvtmu_dd_round_simd: // @fcvtmu_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms d0, d0
+ ret
+.Lfunc_end39:
+ .size fcvtmu_dd_round_simd, .Lfunc_end39-fcvtmu_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_ds_round_simd // -- Begin function fcvtps_ds_round_simd
+ .p2align 2
+ .type fcvtps_ds_round_simd, at function
+fcvtps_ds_round_simd: // @fcvtps_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps d0, s0
+ ret
+.Lfunc_end40:
+ .size fcvtps_ds_round_simd, .Lfunc_end40-fcvtps_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_sd_round_simd // -- Begin function fcvtps_sd_round_simd
+ .p2align 2
+ .type fcvtps_sd_round_simd, at function
+fcvtps_sd_round_simd: // @fcvtps_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps s0, d0
+ ret
+.Lfunc_end41:
+ .size fcvtps_sd_round_simd, .Lfunc_end41-fcvtps_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_ss_round_simd // -- Begin function fcvtps_ss_round_simd
+ .p2align 2
+ .type fcvtps_ss_round_simd, at function
+fcvtps_ss_round_simd: // @fcvtps_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps s0, s0
+ ret
+.Lfunc_end42:
+ .size fcvtps_ss_round_simd, .Lfunc_end42-fcvtps_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_dd_round_simd // -- Begin function fcvtps_dd_round_simd
+ .p2align 2
+ .type fcvtps_dd_round_simd, at function
+fcvtps_dd_round_simd: // @fcvtps_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps d0, d0
+ ret
+.Lfunc_end43:
+ .size fcvtps_dd_round_simd, .Lfunc_end43-fcvtps_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_ds_round_simd // -- Begin function fcvtpu_ds_round_simd
+ .p2align 2
+ .type fcvtpu_ds_round_simd, at function
+fcvtpu_ds_round_simd: // @fcvtpu_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtpu d0, s0
+ ret
+.Lfunc_end44:
+ .size fcvtpu_ds_round_simd, .Lfunc_end44-fcvtpu_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_sd_round_simd // -- Begin function fcvtpu_sd_round_simd
+ .p2align 2
+ .type fcvtpu_sd_round_simd, at function
+fcvtpu_sd_round_simd: // @fcvtpu_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtpu s0, d0
+ ret
+.Lfunc_end45:
+ .size fcvtpu_sd_round_simd, .Lfunc_end45-fcvtpu_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_ss_round_simd // -- Begin function fcvtpu_ss_round_simd
+ .p2align 2
+ .type fcvtpu_ss_round_simd, at function
+fcvtpu_ss_round_simd: // @fcvtpu_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps s0, s0
+ ret
+.Lfunc_end46:
+ .size fcvtpu_ss_round_simd, .Lfunc_end46-fcvtpu_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_dd_round_simd // -- Begin function fcvtpu_dd_round_simd
+ .p2align 2
+ .type fcvtpu_dd_round_simd, at function
+fcvtpu_dd_round_simd: // @fcvtpu_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps d0, d0
+ ret
+.Lfunc_end47:
+ .size fcvtpu_dd_round_simd, .Lfunc_end47-fcvtpu_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_ds_round_simd // -- Begin function fcvtzs_ds_round_simd
+ .p2align 2
+ .type fcvtzs_ds_round_simd, at function
+fcvtzs_ds_round_simd: // @fcvtzs_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, s0
+ ret
+.Lfunc_end48:
+ .size fcvtzs_ds_round_simd, .Lfunc_end48-fcvtzs_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_sd_round_simd // -- Begin function fcvtzs_sd_round_simd
+ .p2align 2
+ .type fcvtzs_sd_round_simd, at function
+fcvtzs_sd_round_simd: // @fcvtzs_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, d0
+ ret
+.Lfunc_end49:
+ .size fcvtzs_sd_round_simd, .Lfunc_end49-fcvtzs_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_ss_round_simd // -- Begin function fcvtzs_ss_round_simd
+ .p2align 2
+ .type fcvtzs_ss_round_simd, at function
+fcvtzs_ss_round_simd: // @fcvtzs_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, s0
+ ret
+.Lfunc_end50:
+ .size fcvtzs_ss_round_simd, .Lfunc_end50-fcvtzs_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_dd_round_simd // -- Begin function fcvtzs_dd_round_simd
+ .p2align 2
+ .type fcvtzs_dd_round_simd, at function
+fcvtzs_dd_round_simd: // @fcvtzs_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end51:
+ .size fcvtzs_dd_round_simd, .Lfunc_end51-fcvtzs_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_ds_round_simd // -- Begin function fcvtzu_ds_round_simd
+ .p2align 2
+ .type fcvtzu_ds_round_simd, at function
+fcvtzu_ds_round_simd: // @fcvtzu_ds_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, s0
+ ret
+.Lfunc_end52:
+ .size fcvtzu_ds_round_simd, .Lfunc_end52-fcvtzu_ds_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_sd_round_simd // -- Begin function fcvtzu_sd_round_simd
+ .p2align 2
+ .type fcvtzu_sd_round_simd, at function
+fcvtzu_sd_round_simd: // @fcvtzu_sd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, d0
+ ret
+.Lfunc_end53:
+ .size fcvtzu_sd_round_simd, .Lfunc_end53-fcvtzu_sd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_ss_round_simd // -- Begin function fcvtzu_ss_round_simd
+ .p2align 2
+ .type fcvtzu_ss_round_simd, at function
+fcvtzu_ss_round_simd: // @fcvtzu_ss_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, s0
+ ret
+.Lfunc_end54:
+ .size fcvtzu_ss_round_simd, .Lfunc_end54-fcvtzu_ss_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_dd_round_simd // -- Begin function fcvtzu_dd_round_simd
+ .p2align 2
+ .type fcvtzu_dd_round_simd, at function
+fcvtzu_dd_round_simd: // @fcvtzu_dd_round_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end55:
+ .size fcvtzu_dd_round_simd, .Lfunc_end55-fcvtzu_dd_round_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_sh_sat_simd // -- Begin function fcvtzs_sh_sat_simd
+ .p2align 2
+ .type fcvtzs_sh_sat_simd, at function
+fcvtzs_sh_sat_simd: // @fcvtzs_sh_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, h0
+ ret
+.Lfunc_end56:
+ .size fcvtzs_sh_sat_simd, .Lfunc_end56-fcvtzs_sh_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_dh_sat_simd // -- Begin function fcvtzs_dh_sat_simd
+ .p2align 2
+ .type fcvtzs_dh_sat_simd, at function
+fcvtzs_dh_sat_simd: // @fcvtzs_dh_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, h0
+ ret
+.Lfunc_end57:
+ .size fcvtzs_dh_sat_simd, .Lfunc_end57-fcvtzs_dh_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_ds_sat_simd // -- Begin function fcvtzs_ds_sat_simd
+ .p2align 2
+ .type fcvtzs_ds_sat_simd, at function
+fcvtzs_ds_sat_simd: // @fcvtzs_ds_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, s0
+ ret
+.Lfunc_end58:
+ .size fcvtzs_ds_sat_simd, .Lfunc_end58-fcvtzs_ds_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_sd_sat_simd // -- Begin function fcvtzs_sd_sat_simd
+ .p2align 2
+ .type fcvtzs_sd_sat_simd, at function
+fcvtzs_sd_sat_simd: // @fcvtzs_sd_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, d0
+ ret
+.Lfunc_end59:
+ .size fcvtzs_sd_sat_simd, .Lfunc_end59-fcvtzs_sd_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_ss_sat_simd // -- Begin function fcvtzs_ss_sat_simd
+ .p2align 2
+ .type fcvtzs_ss_sat_simd, at function
+fcvtzs_ss_sat_simd: // @fcvtzs_ss_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, s0
+ ret
+.Lfunc_end60:
+ .size fcvtzs_ss_sat_simd, .Lfunc_end60-fcvtzs_ss_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_dd_sat_simd // -- Begin function fcvtzs_dd_sat_simd
+ .p2align 2
+ .type fcvtzs_dd_sat_simd, at function
+fcvtzs_dd_sat_simd: // @fcvtzs_dd_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end61:
+ .size fcvtzs_dd_sat_simd, .Lfunc_end61-fcvtzs_dd_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_sh_sat_simd // -- Begin function fcvtzu_sh_sat_simd
+ .p2align 2
+ .type fcvtzu_sh_sat_simd, at function
+fcvtzu_sh_sat_simd: // @fcvtzu_sh_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, h0
+ ret
+.Lfunc_end62:
+ .size fcvtzu_sh_sat_simd, .Lfunc_end62-fcvtzu_sh_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_dh_sat_simd // -- Begin function fcvtzu_dh_sat_simd
+ .p2align 2
+ .type fcvtzu_dh_sat_simd, at function
+fcvtzu_dh_sat_simd: // @fcvtzu_dh_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, h0
+ ret
+.Lfunc_end63:
+ .size fcvtzu_dh_sat_simd, .Lfunc_end63-fcvtzu_dh_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_ds_sat_simd // -- Begin function fcvtzu_ds_sat_simd
+ .p2align 2
+ .type fcvtzu_ds_sat_simd, at function
+fcvtzu_ds_sat_simd: // @fcvtzu_ds_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, s0
+ ret
+.Lfunc_end64:
+ .size fcvtzu_ds_sat_simd, .Lfunc_end64-fcvtzu_ds_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_sd_sat_simd // -- Begin function fcvtzu_sd_sat_simd
+ .p2align 2
+ .type fcvtzu_sd_sat_simd, at function
+fcvtzu_sd_sat_simd: // @fcvtzu_sd_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, d0
+ ret
+.Lfunc_end65:
+ .size fcvtzu_sd_sat_simd, .Lfunc_end65-fcvtzu_sd_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_ss_sat_simd // -- Begin function fcvtzu_ss_sat_simd
+ .p2align 2
+ .type fcvtzu_ss_sat_simd, at function
+fcvtzu_ss_sat_simd: // @fcvtzu_ss_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, s0
+ ret
+.Lfunc_end66:
+ .size fcvtzu_ss_sat_simd, .Lfunc_end66-fcvtzu_ss_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_dd_sat_simd // -- Begin function fcvtzu_dd_sat_simd
+ .p2align 2
+ .type fcvtzu_dd_sat_simd, at function
+fcvtzu_dd_sat_simd: // @fcvtzu_dd_sat_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end67:
+ .size fcvtzu_dd_sat_simd, .Lfunc_end67-fcvtzu_dd_sat_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_sh_simd // -- Begin function fcvtas_sh_simd
+ .p2align 2
+ .type fcvtas_sh_simd, at function
+fcvtas_sh_simd: // @fcvtas_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas s0, h0
+ ret
+.Lfunc_end68:
+ .size fcvtas_sh_simd, .Lfunc_end68-fcvtas_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_dh_simd // -- Begin function fcvtas_dh_simd
+ .p2align 2
+ .type fcvtas_dh_simd, at function
+fcvtas_dh_simd: // @fcvtas_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas d0, h0
+ ret
+.Lfunc_end69:
+ .size fcvtas_dh_simd, .Lfunc_end69-fcvtas_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_ds_simd // -- Begin function fcvtas_ds_simd
+ .p2align 2
+ .type fcvtas_ds_simd, at function
+fcvtas_ds_simd: // @fcvtas_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas d0, s0
+ ret
+.Lfunc_end70:
+ .size fcvtas_ds_simd, .Lfunc_end70-fcvtas_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_sd_simd // -- Begin function fcvtas_sd_simd
+ .p2align 2
+ .type fcvtas_sd_simd, at function
+fcvtas_sd_simd: // @fcvtas_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas s0, d0
+ ret
+.Lfunc_end71:
+ .size fcvtas_sd_simd, .Lfunc_end71-fcvtas_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_ss_simd // -- Begin function fcvtas_ss_simd
+ .p2align 2
+ .type fcvtas_ss_simd, at function
+fcvtas_ss_simd: // @fcvtas_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas s0, s0
+ ret
+.Lfunc_end72:
+ .size fcvtas_ss_simd, .Lfunc_end72-fcvtas_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtas_dd_simd // -- Begin function fcvtas_dd_simd
+ .p2align 2
+ .type fcvtas_dd_simd, at function
+fcvtas_dd_simd: // @fcvtas_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas d0, d0
+ ret
+.Lfunc_end73:
+ .size fcvtas_dd_simd, .Lfunc_end73-fcvtas_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_sh_simd // -- Begin function fcvtau_sh_simd
+ .p2align 2
+ .type fcvtau_sh_simd, at function
+fcvtau_sh_simd: // @fcvtau_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtau s0, h0
+ ret
+.Lfunc_end74:
+ .size fcvtau_sh_simd, .Lfunc_end74-fcvtau_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_dh_simd // -- Begin function fcvtau_dh_simd
+ .p2align 2
+ .type fcvtau_dh_simd, at function
+fcvtau_dh_simd: // @fcvtau_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtau d0, h0
+ ret
+.Lfunc_end75:
+ .size fcvtau_dh_simd, .Lfunc_end75-fcvtau_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_ds_simd // -- Begin function fcvtau_ds_simd
+ .p2align 2
+ .type fcvtau_ds_simd, at function
+fcvtau_ds_simd: // @fcvtau_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtau d0, s0
+ ret
+.Lfunc_end76:
+ .size fcvtau_ds_simd, .Lfunc_end76-fcvtau_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_sd_simd // -- Begin function fcvtau_sd_simd
+ .p2align 2
+ .type fcvtau_sd_simd, at function
+fcvtau_sd_simd: // @fcvtau_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtau s0, d0
+ ret
+.Lfunc_end77:
+ .size fcvtau_sd_simd, .Lfunc_end77-fcvtau_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_ss_simd // -- Begin function fcvtau_ss_simd
+ .p2align 2
+ .type fcvtau_ss_simd, at function
+fcvtau_ss_simd: // @fcvtau_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas s0, s0
+ ret
+.Lfunc_end78:
+ .size fcvtau_ss_simd, .Lfunc_end78-fcvtau_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtau_dd_simd // -- Begin function fcvtau_dd_simd
+ .p2align 2
+ .type fcvtau_dd_simd, at function
+fcvtau_dd_simd: // @fcvtau_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtas d0, d0
+ ret
+.Lfunc_end79:
+ .size fcvtau_dd_simd, .Lfunc_end79-fcvtau_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_sh_simd // -- Begin function fcvtms_sh_simd
+ .p2align 2
+ .type fcvtms_sh_simd, at function
+fcvtms_sh_simd: // @fcvtms_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms s0, h0
+ ret
+.Lfunc_end80:
+ .size fcvtms_sh_simd, .Lfunc_end80-fcvtms_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_dh_simd // -- Begin function fcvtms_dh_simd
+ .p2align 2
+ .type fcvtms_dh_simd, at function
+fcvtms_dh_simd: // @fcvtms_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms d0, h0
+ ret
+.Lfunc_end81:
+ .size fcvtms_dh_simd, .Lfunc_end81-fcvtms_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_ds_simd // -- Begin function fcvtms_ds_simd
+ .p2align 2
+ .type fcvtms_ds_simd, at function
+fcvtms_ds_simd: // @fcvtms_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms d0, s0
+ ret
+.Lfunc_end82:
+ .size fcvtms_ds_simd, .Lfunc_end82-fcvtms_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_sd_simd // -- Begin function fcvtms_sd_simd
+ .p2align 2
+ .type fcvtms_sd_simd, at function
+fcvtms_sd_simd: // @fcvtms_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms s0, d0
+ ret
+.Lfunc_end83:
+ .size fcvtms_sd_simd, .Lfunc_end83-fcvtms_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_ss_simd // -- Begin function fcvtms_ss_simd
+ .p2align 2
+ .type fcvtms_ss_simd, at function
+fcvtms_ss_simd: // @fcvtms_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms s0, s0
+ ret
+.Lfunc_end84:
+ .size fcvtms_ss_simd, .Lfunc_end84-fcvtms_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtms_dd_simd // -- Begin function fcvtms_dd_simd
+ .p2align 2
+ .type fcvtms_dd_simd, at function
+fcvtms_dd_simd: // @fcvtms_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms d0, d0
+ ret
+.Lfunc_end85:
+ .size fcvtms_dd_simd, .Lfunc_end85-fcvtms_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_sh_simd // -- Begin function fcvtmu_sh_simd
+ .p2align 2
+ .type fcvtmu_sh_simd, at function
+fcvtmu_sh_simd: // @fcvtmu_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtmu s0, h0
+ ret
+.Lfunc_end86:
+ .size fcvtmu_sh_simd, .Lfunc_end86-fcvtmu_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_dh_simd // -- Begin function fcvtmu_dh_simd
+ .p2align 2
+ .type fcvtmu_dh_simd, at function
+fcvtmu_dh_simd: // @fcvtmu_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtmu d0, h0
+ ret
+.Lfunc_end87:
+ .size fcvtmu_dh_simd, .Lfunc_end87-fcvtmu_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_ds_simd // -- Begin function fcvtmu_ds_simd
+ .p2align 2
+ .type fcvtmu_ds_simd, at function
+fcvtmu_ds_simd: // @fcvtmu_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtmu d0, s0
+ ret
+.Lfunc_end88:
+ .size fcvtmu_ds_simd, .Lfunc_end88-fcvtmu_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_sd_simd // -- Begin function fcvtmu_sd_simd
+ .p2align 2
+ .type fcvtmu_sd_simd, at function
+fcvtmu_sd_simd: // @fcvtmu_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtmu s0, d0
+ ret
+.Lfunc_end89:
+ .size fcvtmu_sd_simd, .Lfunc_end89-fcvtmu_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_ss_simd // -- Begin function fcvtmu_ss_simd
+ .p2align 2
+ .type fcvtmu_ss_simd, at function
+fcvtmu_ss_simd: // @fcvtmu_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms s0, s0
+ ret
+.Lfunc_end90:
+ .size fcvtmu_ss_simd, .Lfunc_end90-fcvtmu_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtmu_dd_simd // -- Begin function fcvtmu_dd_simd
+ .p2align 2
+ .type fcvtmu_dd_simd, at function
+fcvtmu_dd_simd: // @fcvtmu_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtms d0, d0
+ ret
+.Lfunc_end91:
+ .size fcvtmu_dd_simd, .Lfunc_end91-fcvtmu_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_sh_simd // -- Begin function fcvtps_sh_simd
+ .p2align 2
+ .type fcvtps_sh_simd, at function
+fcvtps_sh_simd: // @fcvtps_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps s0, h0
+ ret
+.Lfunc_end92:
+ .size fcvtps_sh_simd, .Lfunc_end92-fcvtps_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_dh_simd // -- Begin function fcvtps_dh_simd
+ .p2align 2
+ .type fcvtps_dh_simd, at function
+fcvtps_dh_simd: // @fcvtps_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps d0, h0
+ ret
+.Lfunc_end93:
+ .size fcvtps_dh_simd, .Lfunc_end93-fcvtps_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_ds_simd // -- Begin function fcvtps_ds_simd
+ .p2align 2
+ .type fcvtps_ds_simd, at function
+fcvtps_ds_simd: // @fcvtps_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps d0, s0
+ ret
+.Lfunc_end94:
+ .size fcvtps_ds_simd, .Lfunc_end94-fcvtps_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_sd_simd // -- Begin function fcvtps_sd_simd
+ .p2align 2
+ .type fcvtps_sd_simd, at function
+fcvtps_sd_simd: // @fcvtps_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps s0, d0
+ ret
+.Lfunc_end95:
+ .size fcvtps_sd_simd, .Lfunc_end95-fcvtps_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_ss_simd // -- Begin function fcvtps_ss_simd
+ .p2align 2
+ .type fcvtps_ss_simd, at function
+fcvtps_ss_simd: // @fcvtps_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps s0, s0
+ ret
+.Lfunc_end96:
+ .size fcvtps_ss_simd, .Lfunc_end96-fcvtps_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtps_dd_simd // -- Begin function fcvtps_dd_simd
+ .p2align 2
+ .type fcvtps_dd_simd, at function
+fcvtps_dd_simd: // @fcvtps_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps d0, d0
+ ret
+.Lfunc_end97:
+ .size fcvtps_dd_simd, .Lfunc_end97-fcvtps_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_sh_simd // -- Begin function fcvtpu_sh_simd
+ .p2align 2
+ .type fcvtpu_sh_simd, at function
+fcvtpu_sh_simd: // @fcvtpu_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtpu s0, h0
+ ret
+.Lfunc_end98:
+ .size fcvtpu_sh_simd, .Lfunc_end98-fcvtpu_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_dh_simd // -- Begin function fcvtpu_dh_simd
+ .p2align 2
+ .type fcvtpu_dh_simd, at function
+fcvtpu_dh_simd: // @fcvtpu_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtpu d0, h0
+ ret
+.Lfunc_end99:
+ .size fcvtpu_dh_simd, .Lfunc_end99-fcvtpu_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_ds_simd // -- Begin function fcvtpu_ds_simd
+ .p2align 2
+ .type fcvtpu_ds_simd, at function
+fcvtpu_ds_simd: // @fcvtpu_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtpu d0, s0
+ ret
+.Lfunc_end100:
+ .size fcvtpu_ds_simd, .Lfunc_end100-fcvtpu_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_sd_simd // -- Begin function fcvtpu_sd_simd
+ .p2align 2
+ .type fcvtpu_sd_simd, at function
+fcvtpu_sd_simd: // @fcvtpu_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtpu s0, d0
+ ret
+.Lfunc_end101:
+ .size fcvtpu_sd_simd, .Lfunc_end101-fcvtpu_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_ss_simd // -- Begin function fcvtpu_ss_simd
+ .p2align 2
+ .type fcvtpu_ss_simd, at function
+fcvtpu_ss_simd: // @fcvtpu_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps s0, s0
+ ret
+.Lfunc_end102:
+ .size fcvtpu_ss_simd, .Lfunc_end102-fcvtpu_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtpu_dd_simd // -- Begin function fcvtpu_dd_simd
+ .p2align 2
+ .type fcvtpu_dd_simd, at function
+fcvtpu_dd_simd: // @fcvtpu_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtps d0, d0
+ ret
+.Lfunc_end103:
+ .size fcvtpu_dd_simd, .Lfunc_end103-fcvtpu_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_sh_simd // -- Begin function fcvtzs_sh_simd
+ .p2align 2
+ .type fcvtzs_sh_simd, at function
+fcvtzs_sh_simd: // @fcvtzs_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, h0
+ ret
+.Lfunc_end104:
+ .size fcvtzs_sh_simd, .Lfunc_end104-fcvtzs_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_dh_simd // -- Begin function fcvtzs_dh_simd
+ .p2align 2
+ .type fcvtzs_dh_simd, at function
+fcvtzs_dh_simd: // @fcvtzs_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, h0
+ ret
+.Lfunc_end105:
+ .size fcvtzs_dh_simd, .Lfunc_end105-fcvtzs_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_ds_simd // -- Begin function fcvtzs_ds_simd
+ .p2align 2
+ .type fcvtzs_ds_simd, at function
+fcvtzs_ds_simd: // @fcvtzs_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, s0
+ ret
+.Lfunc_end106:
+ .size fcvtzs_ds_simd, .Lfunc_end106-fcvtzs_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_sd_simd // -- Begin function fcvtzs_sd_simd
+ .p2align 2
+ .type fcvtzs_sd_simd, at function
+fcvtzs_sd_simd: // @fcvtzs_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, d0
+ ret
+.Lfunc_end107:
+ .size fcvtzs_sd_simd, .Lfunc_end107-fcvtzs_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_ss_simd // -- Begin function fcvtzs_ss_simd
+ .p2align 2
+ .type fcvtzs_ss_simd, at function
+fcvtzs_ss_simd: // @fcvtzs_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs s0, s0
+ ret
+.Lfunc_end108:
+ .size fcvtzs_ss_simd, .Lfunc_end108-fcvtzs_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_dd_simd // -- Begin function fcvtzs_dd_simd
+ .p2align 2
+ .type fcvtzs_dd_simd, at function
+fcvtzs_dd_simd: // @fcvtzs_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end109:
+ .size fcvtzs_dd_simd, .Lfunc_end109-fcvtzs_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_sh_simd // -- Begin function fcvtzu_sh_simd
+ .p2align 2
+ .type fcvtzu_sh_simd, at function
+fcvtzu_sh_simd: // @fcvtzu_sh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, h0
+ ret
+.Lfunc_end110:
+ .size fcvtzu_sh_simd, .Lfunc_end110-fcvtzu_sh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_dh_simd // -- Begin function fcvtzu_dh_simd
+ .p2align 2
+ .type fcvtzu_dh_simd, at function
+fcvtzu_dh_simd: // @fcvtzu_dh_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, h0
+ ret
+.Lfunc_end111:
+ .size fcvtzu_dh_simd, .Lfunc_end111-fcvtzu_dh_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_ds_simd // -- Begin function fcvtzu_ds_simd
+ .p2align 2
+ .type fcvtzu_ds_simd, at function
+fcvtzu_ds_simd: // @fcvtzu_ds_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, s0
+ ret
+.Lfunc_end112:
+ .size fcvtzu_ds_simd, .Lfunc_end112-fcvtzu_ds_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_sd_simd // -- Begin function fcvtzu_sd_simd
+ .p2align 2
+ .type fcvtzu_sd_simd, at function
+fcvtzu_sd_simd: // @fcvtzu_sd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, d0
+ ret
+.Lfunc_end113:
+ .size fcvtzu_sd_simd, .Lfunc_end113-fcvtzu_sd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_ss_simd // -- Begin function fcvtzu_ss_simd
+ .p2align 2
+ .type fcvtzu_ss_simd, at function
+fcvtzu_ss_simd: // @fcvtzu_ss_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu s0, s0
+ ret
+.Lfunc_end114:
+ .size fcvtzu_ss_simd, .Lfunc_end114-fcvtzu_ss_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_dd_simd // -- Begin function fcvtzu_dd_simd
+ .p2align 2
+ .type fcvtzu_dd_simd, at function
+fcvtzu_dd_simd: // @fcvtzu_dd_simd
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, d0
+ ret
+.Lfunc_end115:
+ .size fcvtzu_dd_simd, .Lfunc_end115-fcvtzu_dd_simd
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_scalar_to_vector_h // -- Begin function fcvtzs_scalar_to_vector_h
+ .p2align 2
+ .type fcvtzs_scalar_to_vector_h, at function
+fcvtzs_scalar_to_vector_h: // @fcvtzs_scalar_to_vector_h
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, h0
+ ret
+.Lfunc_end116:
+ .size fcvtzs_scalar_to_vector_h, .Lfunc_end116-fcvtzs_scalar_to_vector_h
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_scalar_to_vector_s // -- Begin function fcvtzs_scalar_to_vector_s
+ .p2align 2
+ .type fcvtzs_scalar_to_vector_s, at function
+fcvtzs_scalar_to_vector_s: // @fcvtzs_scalar_to_vector_s
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, s0
+ ret
+.Lfunc_end117:
+ .size fcvtzs_scalar_to_vector_s, .Lfunc_end117-fcvtzs_scalar_to_vector_s
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_scalar_to_vector_d // -- Begin function fcvtzs_scalar_to_vector_d
+ .p2align 2
+ .type fcvtzs_scalar_to_vector_d, at function
+fcvtzs_scalar_to_vector_d: // @fcvtzs_scalar_to_vector_d
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, d0
+ ret
+.Lfunc_end118:
+ .size fcvtzs_scalar_to_vector_d, .Lfunc_end118-fcvtzs_scalar_to_vector_d
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_scalar_to_vector_h // -- Begin function fcvtzu_scalar_to_vector_h
+ .p2align 2
+ .type fcvtzu_scalar_to_vector_h, at function
+fcvtzu_scalar_to_vector_h: // @fcvtzu_scalar_to_vector_h
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, h0
+ ret
+.Lfunc_end119:
+ .size fcvtzu_scalar_to_vector_h, .Lfunc_end119-fcvtzu_scalar_to_vector_h
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_scalar_to_vector_s // -- Begin function fcvtzu_scalar_to_vector_s
+ .p2align 2
+ .type fcvtzu_scalar_to_vector_s, at function
+fcvtzu_scalar_to_vector_s: // @fcvtzu_scalar_to_vector_s
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, s0
+ ret
+.Lfunc_end120:
+ .size fcvtzu_scalar_to_vector_s, .Lfunc_end120-fcvtzu_scalar_to_vector_s
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_scalar_to_vector_d // -- Begin function fcvtzu_scalar_to_vector_d
+ .p2align 2
+ .type fcvtzu_scalar_to_vector_d, at function
+fcvtzu_scalar_to_vector_d: // @fcvtzu_scalar_to_vector_d
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, d0
+ ret
+.Lfunc_end121:
+ .size fcvtzu_scalar_to_vector_d, .Lfunc_end121-fcvtzu_scalar_to_vector_d
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_scalar_to_vector_h_strict // -- Begin function fcvtzs_scalar_to_vector_h_strict
+ .p2align 2
+ .type fcvtzs_scalar_to_vector_h_strict, at function
+fcvtzs_scalar_to_vector_h_strict: // @fcvtzs_scalar_to_vector_h_strict
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, h0
+ ret
+.Lfunc_end122:
+ .size fcvtzs_scalar_to_vector_h_strict, .Lfunc_end122-fcvtzs_scalar_to_vector_h_strict
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzs_scalar_to_vector_s_strict // -- Begin function fcvtzs_scalar_to_vector_s_strict
+ .p2align 2
+ .type fcvtzs_scalar_to_vector_s_strict, at function
+fcvtzs_scalar_to_vector_s_strict: // @fcvtzs_scalar_to_vector_s_strict
+ .cfi_startproc
+// %bb.0:
+ fcvtzs d0, s0
+ ret
+.Lfunc_end123:
+ .size fcvtzs_scalar_to_vector_s_strict, .Lfunc_end123-fcvtzs_scalar_to_vector_s_strict
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_scalar_to_vector_h_strict // -- Begin function fcvtzu_scalar_to_vector_h_strict
+ .p2align 2
+ .type fcvtzu_scalar_to_vector_h_strict, at function
+fcvtzu_scalar_to_vector_h_strict: // @fcvtzu_scalar_to_vector_h_strict
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, h0
+ ret
+.Lfunc_end124:
+ .size fcvtzu_scalar_to_vector_h_strict, .Lfunc_end124-fcvtzu_scalar_to_vector_h_strict
+ .cfi_endproc
+ // -- End function
+ .globl fcvtzu_scalar_to_vector_s_strict // -- Begin function fcvtzu_scalar_to_vector_s_strict
+ .p2align 2
+ .type fcvtzu_scalar_to_vector_s_strict, at function
+fcvtzu_scalar_to_vector_s_strict: // @fcvtzu_scalar_to_vector_s_strict
+ .cfi_startproc
+// %bb.0:
+ fcvtzu d0, s0
+ ret
+.Lfunc_end125:
+ .size fcvtzu_scalar_to_vector_s_strict, .Lfunc_end125-fcvtzu_scalar_to_vector_s_strict
+ .cfi_endproc
+ // -- End function
+ .section ".note.GNU-stack","", at progbits
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
index b1b9fcf8a8b3c..8b8f23a049107 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
@@ -4,7 +4,7 @@
;
-; Intriniscs
+; Intriniscs (bitcast)
;
define float @fcvtas_1s1d_simd(double %A) nounwind {
@@ -607,3 +607,335 @@ define float @fcvtzu_1s1s_simd(float %a) {
%d = bitcast i32 %vcvtah_s32_f32 to float
ret float %d
}
+
+;
+; Intriniscs (scalar_to_vector)
+;
+
+define <1 x i64> @fcvtas_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtas_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtas_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtas_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtas_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtas_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtau_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtau_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtau_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtau_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtau_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtau_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtms_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtms_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtms_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtms_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtms_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtms_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtmu_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtmu_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtmu_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtmu_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtmu_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtmu_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtns_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtns_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtns.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtns_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtns_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtns_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtns_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtnu_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtnu_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtnu_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtnu_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtnu_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtnu_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtps_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtps_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtps_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtps_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtps_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtps_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtpu_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtpu_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtpu_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtpu_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtpu_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtpu_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtzs_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtzs_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtzs_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtzs_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzs_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtzs_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
+
+
+
+define <1 x i64> @fcvtzu_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtzu_1d1s_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, s0
+; CHECK-NEXT: ret
+ %i = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float %A)
+ %vec = insertelement <1 x i64> poison, i64 %i, i32 0
+ ret <1 x i64> %vec
+}
+
+
+define <1 x i64> @fcvtzu_1d1h_scalar_to_vector_simd(half %a) {
+; CHECK-LABEL: fcvtzu_1d1h_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, h0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtzu.i64.f16(half %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f16, i32 0
+ ret <1 x i64> %vec
+}
+
+define <1 x i64> @fcvtzu_1d1d_scalar_to_vector_simd(double %a) {
+; CHECK-LABEL: fcvtzu_1d1d_scalar_to_vector_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, d0
+; CHECK-NEXT: ret
+ %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %a)
+ %vec = insertelement <1 x i64> poison, i64 %vcvtah_s64_f64, i32 0
+ ret <1 x i64> %vec
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll b/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
index b580c4921fb66..35f62e52ffd76 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
@@ -21,8 +21,7 @@ define double @bar(ptr %iVals, ptr %fVals, ptr %dVals) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr d0, [x2, #128]
; CHECK-NEXT: frinti d0, d0
-; CHECK-NEXT: fcvtzs x8, d0
-; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: sri d0, d0, #1
; CHECK-NEXT: scvtf.2d v0, v0, #1
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index d8f370884c84a..c2f39fb14ee24 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -980,18 +980,11 @@ define <1 x double> @test_bitcasti64tov1f64(i64 %in) {
}
define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {
-; CHECK-SD-LABEL: test_bitcastv8i8tov1f64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: neg v0.8b, v0.8b
-; CHECK-SD-NEXT: fcvtzs x8, d0
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_bitcastv8i8tov1f64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: neg v0.8b, v0.8b
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_bitcastv8i8tov1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v0.8b, v0.8b
+; CHECK-NEXT: fcvtzs d0, d0
+; CHECK-NEXT: ret
%sub.i = sub <8 x i8> zeroinitializer, %a
%1 = bitcast <8 x i8> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -999,18 +992,11 @@ define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {
}
define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {
-; CHECK-SD-LABEL: test_bitcastv4i16tov1f64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: neg v0.4h, v0.4h
-; CHECK-SD-NEXT: fcvtzs x8, d0
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_bitcastv4i16tov1f64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: neg v0.4h, v0.4h
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_bitcastv4i16tov1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v0.4h, v0.4h
+; CHECK-NEXT: fcvtzs d0, d0
+; CHECK-NEXT: ret
%sub.i = sub <4 x i16> zeroinitializer, %a
%1 = bitcast <4 x i16> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -1018,18 +1004,11 @@ define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {
}
define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 {
-; CHECK-SD-LABEL: test_bitcastv2i32tov1f64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: neg v0.2s, v0.2s
-; CHECK-SD-NEXT: fcvtzs x8, d0
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_bitcastv2i32tov1f64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: neg v0.2s, v0.2s
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_bitcastv2i32tov1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v0.2s, v0.2s
+; CHECK-NEXT: fcvtzs d0, d0
+; CHECK-NEXT: ret
%sub.i = sub <2 x i32> zeroinitializer, %a
%1 = bitcast <2 x i32> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
@@ -1040,8 +1019,7 @@ define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 {
; CHECK-SD-LABEL: test_bitcastv1i64tov1f64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: neg d0, d0
-; CHECK-SD-NEXT: fcvtzs x8, d0
-; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fcvtzs d0, d0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_bitcastv1i64tov1f64:
@@ -1061,8 +1039,7 @@ define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 {
; CHECK-LABEL: test_bitcastv2f32tov1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: fneg v0.2s, v0.2s
-; CHECK-NEXT: fcvtzs x8, d0
-; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
%sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a
%1 = bitcast <2 x float> %sub.i to <1 x double>
diff --git a/llvm/test/CodeGen/AArch64/arm64-vcvt.ll b/llvm/test/CodeGen/AArch64/arm64-vcvt.ll
index 1e0cfa0201263..dcb3b9b24627b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vcvt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vcvt.ll
@@ -359,16 +359,10 @@ define <2 x i64> @fcvtzs_2d(<2 x double> %A) nounwind {
; FIXME: Generate "fcvtzs d0, d0"?
define <1 x i64> @fcvtzs_1d(<1 x double> %A) nounwind {
-; CHECK-SD-LABEL: fcvtzs_1d:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs x8, d0
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzs_1d:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fcvtzs d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzs_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, d0
+; CHECK-NEXT: ret
%tmp3 = fptosi <1 x double> %A to <1 x i64>
ret <1 x i64> %tmp3
}
@@ -443,16 +437,10 @@ define <2 x i64> @fcvtzu_2d(<2 x double> %A) nounwind {
; FIXME: Generate "fcvtzu d0, d0"?
define <1 x i64> @fcvtzu_1d(<1 x double> %A) nounwind {
-; CHECK-SD-LABEL: fcvtzu_1d:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu x8, d0
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fcvtzu_1d:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fcvtzu d0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fcvtzu_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, d0
+; CHECK-NEXT: ret
%tmp3 = fptoui <1 x double> %A to <1 x i64>
ret <1 x i64> %tmp3
}
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
index c3da22757f1d2..0b05e00a1b0db 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
@@ -717,8 +717,7 @@ define <1 x i32> @fptoui_v1i32_v1f64(<1 x double> %x) #0 {
define <1 x i64> @fptosi_v1i64_v1f64(<1 x double> %x) #0 {
; CHECK-LABEL: fptosi_v1i64_v1f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs x8, d0
-; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
%val = call <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f64(<1 x double> %x, metadata !"fpexcept.strict") #0
ret <1 x i64> %val
@@ -727,8 +726,7 @@ define <1 x i64> @fptosi_v1i64_v1f64(<1 x double> %x) #0 {
define <1 x i64> @fptoui_v1i64_v1f64(<1 x double> %x) #0 {
; CHECK-LABEL: fptoui_v1i64_v1f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu x8, d0
-; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
%val = call <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f64(<1 x double> %x, metadata !"fpexcept.strict") #0
ret <1 x i64> %val
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
index c8f6d98f5a63f..312d158cfb2b6 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
@@ -815,8 +815,7 @@ define void @fcvtzu_v32f64_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 {
define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) vscale_range(2,0) #0 {
; CHECK-LABEL: fcvtzu_v1f64_v1i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu x8, d0
-; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
%res = fptoui <1 x double> %op1 to <1 x i64>
ret <1 x i64> %res
@@ -1710,8 +1709,7 @@ define void @fcvtzs_v32f64_v32i32(ptr %a, ptr %b) vscale_range(16,0) #0 {
define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) vscale_range(2,0) #0 {
; CHECK-LABEL: fcvtzs_v1f64_v1i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs x8, d0
-; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
%res = fptosi <1 x double> %op1 to <1 x i64>
ret <1 x i64> %res
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