[llvm] [RISCV] Use pli.b and pli.h in RISCVMatInt with P extension on RV32. (PR #172803)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

On RV32, we don't need to check that the upper and lower 32 bits match.

---
Full diff: https://github.com/llvm/llvm-project/pull/172803.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp (+1-1) 
- (modified) llvm/test/CodeGen/RISCV/rv32p.ll (+16) 
- (modified) llvm/test/CodeGen/RISCV/rv64p.ll (+42) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 3bbd2d2b3a0fd..325e3a03db6c0 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -87,7 +87,7 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
     int16_t Bit15To0 = Bit31To0;
     int8_t Bit15To8 = Bit15To0 >> 8;
     int8_t Bit7To0 = Bit15To0;
-    if (Bit63To32 == Bit31To0) {
+    if (!IsRV64 || Bit63To32 == Bit31To0) {
       if (IsRV64 && isInt<10>(Bit63To32)) {
         Res.emplace_back(RISCV::PLI_W, Bit63To32);
         return;
diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll
index 4fa9a572d609d..c9111a1a24f98 100644
--- a/llvm/test/CodeGen/RISCV/rv32p.ll
+++ b/llvm/test/CodeGen/RISCV/rv32p.ll
@@ -35,6 +35,22 @@ define i32 @li_imm() {
   ret i32 -1
 }
 
+define i32 @pli_b_i32(ptr %p) {
+; CHECK-LABEL: pli_b_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.b a0, 5
+; CHECK-NEXT:    ret
+  ret i32 u0x05050505
+}
+
+define i32 @pli_h_i32(ptr %p) {
+; CHECK-LABEL: pli_h_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.h a0, -64
+; CHECK-NEXT:    ret
+  ret i32 u0xffc0ffc0
+}
+
 define void @pli_b_store_i32(ptr %p) {
 ; CHECK-LABEL: pli_b_store_i32:
 ; CHECK:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
index bff9771299a88..22dba6501f68c 100644
--- a/llvm/test/CodeGen/RISCV/rv64p.ll
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -48,6 +48,48 @@ define i64 @li_imm() {
   ret i64 -1
 }
 
+define i32 @pli_b_i32() {
+; CHECK-LABEL: pli_b_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 20560
+; CHECK-NEXT:    addi a0, a0, 1285
+; CHECK-NEXT:    ret
+  ret i32 u0x05050505
+}
+
+define i64 @pli_b_i64() {
+; CHECK-LABEL: pli_b_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.b a0, -128
+; CHECK-NEXT:    ret
+  ret i64 u0x8080808080808080
+}
+
+define i32 @pli_h_i32() {
+; CHECK-LABEL: pli_h_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1047840
+; CHECK-NEXT:    addi a0, a0, -47
+; CHECK-NEXT:    ret
+  ret i32 u0xffd1ffd1
+}
+
+define i64 @pli_h_i64() {
+; CHECK-LABEL: pli_h_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.h a0, 291
+; CHECK-NEXT:    ret
+  ret i64 u0x0123012301230123
+}
+
+define i64 @pli_w_i64() {
+; CHECK-LABEL: pli_w_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.w a0, -292
+; CHECK-NEXT:    ret
+  ret i64 u0xfffffedcfffffedc
+}
+
 define void @pli_b_store_i32(ptr %p) {
 ; CHECK-LABEL: pli_b_store_i32:
 ; CHECK:       # %bb.0:

``````````

</details>


https://github.com/llvm/llvm-project/pull/172803