[llvm] [SDAG] Shrink (abd? (?ext x) (?ext y)) (PR #171865)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 17 08:04:41 PST 2025
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/171865
>From 24372a12f795a54595b0c84b068da74ba34d880f Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Thu, 11 Dec 2025 18:35:26 +0200
Subject: [PATCH 1/2] [SDAG] Shrink (abds (sext x) (sext y))
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 17 ++-
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 128 ++++++++++++++++++
2 files changed, 144 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6a99d4e29b64f..e7e36f8093060 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5771,7 +5771,7 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
if (N0 == N1)
return DAG.getConstant(0, DL, VT);
- SDValue X;
+ SDValue X, Y;
// fold (abds x, 0) -> abs x
if (sd_match(N, m_c_BinOp(ISD::ABDS, m_Value(X), m_Zero())) &&
@@ -5787,6 +5787,21 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
+ // fold (abds (?ext x), (?ext y)) -> (zext (abd? x, y))
+ if (sd_match(N, m_BinOp(ISD::ABDU, m_ZExt(m_Value(X)), m_ZExt(m_Value(Y)))) ||
+ sd_match(N, m_BinOp(ISD::ABDS, m_SExt(m_Value(X)), m_SExt(m_Value(Y))))) {
+ EVT SmallVT = X.getScalarValueSizeInBits() > Y.getScalarValueSizeInBits()
+ ? X.getValueType()
+ : Y.getValueType();
+ if (!LegalOperations || hasOperation(Opcode, SmallVT)) {
+ SDValue ExtedX = DAG.getExtOrTrunc(X, SDLoc(X), SmallVT, N0->getOpcode());
+ SDValue ExtedY = DAG.getExtOrTrunc(Y, SDLoc(Y), SmallVT, N0->getOpcode());
+ SDValue SmallABD = DAG.getNode(Opcode, DL, SmallVT, {ExtedX, ExtedY});
+ SDValue ZExted = DAG.getZExtOrTrunc(SmallABD, DL, VT);
+ return ZExted;
+ }
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index a3f4722e14406..4d5542ab2d2e6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1952,3 +1952,131 @@ define <8 x i16> @pr88784_fixed(<8 x i8> %l0, <8 x i8> %l1, <8 x i16> %l2) {
ret <8 x i16> %l9
}
+define <16 x i16> @sabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: sabd16b_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sabd.16b v0, v0, v1
+; CHECK-SD-NEXT: ushll2.8h v1, v0, #0
+; CHECK-SD-NEXT: ushll.8h v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sabd16b_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v2, v0, #0
+; CHECK-GI-NEXT: sshll.8h v3, v1, #0
+; CHECK-GI-NEXT: sshll2.8h v4, v0, #0
+; CHECK-GI-NEXT: sshll2.8h v5, v1, #0
+; CHECK-GI-NEXT: ssubl.8h v6, v0, v1
+; CHECK-GI-NEXT: ssubl2.8h v7, v0, v1
+; CHECK-GI-NEXT: cmgt.8h v2, v3, v2
+; CHECK-GI-NEXT: cmgt.8h v3, v5, v4
+; CHECK-GI-NEXT: ssubl.8h v4, v1, v0
+; CHECK-GI-NEXT: ssubl2.8h v1, v1, v0
+; CHECK-GI-NEXT: mov.16b v0, v2
+; CHECK-GI-NEXT: bif.16b v1, v7, v3
+; CHECK-GI-NEXT: bsl.16b v0, v4, v6
+; CHECK-GI-NEXT: ret
+ %aext = sext <16 x i8> %a to <16 x i16>
+ %bext = sext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp slt <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
+
+define <16 x i16> @uabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: uabd16b_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uabd.16b v0, v0, v1
+; CHECK-SD-NEXT: ushll2.8h v1, v0, #0
+; CHECK-SD-NEXT: ushll.8h v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uabd16b_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll.8h v2, v0, #0
+; CHECK-GI-NEXT: ushll.8h v3, v1, #0
+; CHECK-GI-NEXT: ushll2.8h v4, v0, #0
+; CHECK-GI-NEXT: ushll2.8h v5, v1, #0
+; CHECK-GI-NEXT: usubl.8h v6, v0, v1
+; CHECK-GI-NEXT: usubl2.8h v7, v0, v1
+; CHECK-GI-NEXT: cmhi.8h v2, v3, v2
+; CHECK-GI-NEXT: cmhi.8h v3, v5, v4
+; CHECK-GI-NEXT: usubl.8h v4, v1, v0
+; CHECK-GI-NEXT: usubl2.8h v1, v1, v0
+; CHECK-GI-NEXT: mov.16b v0, v2
+; CHECK-GI-NEXT: bif.16b v1, v7, v3
+; CHECK-GI-NEXT: bsl.16b v0, v4, v6
+; CHECK-GI-NEXT: ret
+ %aext = zext <16 x i8> %a to <16 x i16>
+ %bext = zext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp ult <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ ret <16 x i16> %absel
+}
+
+define <16 x i16> @sabd16b_i16_ext(<16 x i16> %aext, <16 x i8> %b) {
+; CHECK-SD-LABEL: sabd16b_i16_ext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll.8h v3, v2, #0
+; CHECK-SD-NEXT: sshll2.8h v2, v2, #0
+; CHECK-SD-NEXT: sabd.8h v1, v1, v2
+; CHECK-SD-NEXT: sabd.8h v0, v0, v3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sabd16b_i16_ext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v3, v2, #0
+; CHECK-GI-NEXT: sshll2.8h v4, v2, #0
+; CHECK-GI-NEXT: ssubw.8h v5, v0, v2
+; CHECK-GI-NEXT: ssubw2.8h v2, v1, v2
+; CHECK-GI-NEXT: cmgt.8h v6, v3, v0
+; CHECK-GI-NEXT: cmgt.8h v7, v4, v1
+; CHECK-GI-NEXT: sub.8h v0, v3, v0
+; CHECK-GI-NEXT: sub.8h v1, v4, v1
+; CHECK-GI-NEXT: bif.16b v0, v5, v6
+; CHECK-GI-NEXT: bif.16b v1, v2, v7
+; CHECK-GI-NEXT: ret
+ %bext = sext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp slt <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
+
+define <16 x i16> @uabd16b_i16_ext(<16 x i16> %aext, <16 x i8> %b) {
+; CHECK-SD-LABEL: uabd16b_i16_ext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll.8h v3, v2, #0
+; CHECK-SD-NEXT: ushll2.8h v2, v2, #0
+; CHECK-SD-NEXT: uabd.8h v1, v1, v2
+; CHECK-SD-NEXT: uabd.8h v0, v0, v3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uabd16b_i16_ext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll.8h v3, v2, #0
+; CHECK-GI-NEXT: ushll2.8h v4, v2, #0
+; CHECK-GI-NEXT: usubw.8h v5, v0, v2
+; CHECK-GI-NEXT: usubw2.8h v2, v1, v2
+; CHECK-GI-NEXT: cmhi.8h v6, v3, v0
+; CHECK-GI-NEXT: cmhi.8h v7, v4, v1
+; CHECK-GI-NEXT: sub.8h v0, v3, v0
+; CHECK-GI-NEXT: sub.8h v1, v4, v1
+; CHECK-GI-NEXT: bif.16b v0, v5, v6
+; CHECK-GI-NEXT: bif.16b v1, v2, v7
+; CHECK-GI-NEXT: ret
+ %bext = zext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp ult <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
>From aefe1fc0e6a4a41b7e7ba08251bcbc2db8330d21 Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Fri, 12 Dec 2025 15:43:05 +0200
Subject: [PATCH 2/2] Better comment (Thanks, Simon!)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e7e36f8093060..6b07f413402f1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5787,7 +5787,7 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
- // fold (abds (?ext x), (?ext y)) -> (zext (abd? x, y))
+ // fold (abd? (?ext x), (?ext y)) -> (zext (abd? x, y))
if (sd_match(N, m_BinOp(ISD::ABDU, m_ZExt(m_Value(X)), m_ZExt(m_Value(Y)))) ||
sd_match(N, m_BinOp(ISD::ABDS, m_SExt(m_Value(X)), m_SExt(m_Value(Y))))) {
EVT SmallVT = X.getScalarValueSizeInBits() > Y.getScalarValueSizeInBits()
More information about the llvm-commits
mailing list