[llvm] [RISCV] Handle codegen for Big Endian (PR #172668)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVSubtarget.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 52ded7525..a43ff86b7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8500,14 +8500,13 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       if (!Subtarget.isLittleEndian())
         std::swap(Lo, Hi);
 
-      SDValue LoStore = DAG.getStore(Chain, DL, Lo, BasePtr,
-                                Store->getPointerInfo(), Store->getBaseAlign(),
-                                Store->getMemOperand()->getFlags());
+      SDValue LoStore = DAG.getStore(
+          Chain, DL, Lo, BasePtr, Store->getPointerInfo(),
+          Store->getBaseAlign(), Store->getMemOperand()->getFlags());
       BasePtr = DAG.getObjectPtrOffset(DL, BasePtr, TypeSize::getFixed(4));
-      SDValue HiStore = DAG.getStore(Chain, DL, Hi, BasePtr,
-                                Store->getPointerInfo().getWithOffset(4),
-                                Store->getBaseAlign(),
-                                Store->getMemOperand()->getFlags());
+      SDValue HiStore = DAG.getStore(
+          Chain, DL, Hi, BasePtr, Store->getPointerInfo().getWithOffset(4),
+          Store->getBaseAlign(), Store->getMemOperand()->getFlags());
       return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, LoStore, HiStore);
     }
     if (VT == MVT::i64) {
@@ -22722,7 +22721,8 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
   MachineMemOperand *MMOHi = MF.getMachineMemOperand(
       MPI.getWithOffset(4), MachineMemOperand::MOStore, 4, Align(8));
 
-  // For big-endian, store the high part at offset 0 and the low part at offset 4.
+  // For big-endian, store the high part at offset 0 and the low part at
+  // offset 4.
   if (!Subtarget.isLittleEndian()) {
     BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
         .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 462ba1115..87227a9d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -108,8 +108,7 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
                                StringRef ABIName, unsigned RVVVectorBitsMin,
                                unsigned RVVVectorBitsMax,
                                const TargetMachine &TM)
-    : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
-      TargetTriple(TT),
+    : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT),
       RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
       FrameLowering(
           initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index a5fc8f0f6..656e7603e 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -222,9 +222,7 @@ public:
   }
 
   bool is64Bit() const { return IsRV64; }
-  bool isLittleEndian() const {
-    return TargetTriple.isLittleEndian();
-  }
+  bool isLittleEndian() const { return TargetTriple.isLittleEndian(); }
   MVT getXLenVT() const {
     return is64Bit() ? MVT::i64 : MVT::i32;
   }

``````````

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https://github.com/llvm/llvm-project/pull/172668