[llvm] [AMDGPU] Allow allocation of lo128 registers from all banks (PR #172614)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 17 01:02:59 PST 2025
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/172614
We can encode 16-bit operands in a short form for VGPRs [0..127].
When we have 1K registers available we can in fact allocate 4
times more from all 4 banks. That, however, requires an allocatable
class for these operands. When for most of the instructions it will
result in the VOP3 longer form, for V_FMAAMK/FMADAK_F16 it will
simply prohibit the encoding because these do not have VOP3 forms.
A straight forward solution would be to create a register class
with all registers having bit 8 of the encoding zero, i.e. to
create a register class with holes punched in it: [0-127, 256-383,
512-639, 768-895]. LLVM, however, does not like register classes
with punched holes when they also have subregisters. The cross-
product of all classes explodes and some combinations of a 'class
having a common subreg with another' becomeing impossible. Just
doing so explodes our register info to 4+Gb, uncompilable too.
The solution proposed is to define _lo128 RC with contigous 896
VGPRs, but the allocation order of it hiding prohibited registers.
That keeps generated register info a reasonable size (+~50%).
The same is needed to VGPR_16_Lo128 in true16 mode.
In general we could later reuse VGPR_32 with AltOrderSelect, but
we would need to pass there operand type and deal with the AsmParser.
One other consideration is that we can allocate a register leaving
a hole of the whole 128 registers, but a subsequent patch can fix
it, i.e. by the time of the RA we really know estimated register
pressure and can further limit allocation order.
For the short: w/o it we either have spilling when we have VGPRs
available, or outright have 'run out of registers' when we have
a lot of 16-bit registers used, a lot of budget, but we cannot
encode it.
>From e1a1b8fd4aa8b900203edd06c32a4b57902e58b5 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Mon, 15 Dec 2025 16:39:40 -0800
Subject: [PATCH] [AMDGPU] Allow allocation of lo128 registers from all banks
We can encode 16-bit operands in a short form for VGPRs [0..127].
When we have 1K registers available we can in fact allocate 4
times more from all 4 banks. That, however, requires an allocatable
class for these operands. When for most of the instructions it will
result in the VOP3 longer form, for V_FMAAMK/FMADAK_F16 it will
simply prohibit the encoding because these do not have VOP3 forms.
A straight forward solution would be to create a register class
with all registers having bit 8 of the encoding zero, i.e. to
create a register class with holes punched in it: [0-127, 256-383,
512-639, 768-895]. LLVM, however, does not like register classes
with punched holes when they also have subregisters. The cross-
product of all classes explodes and some combinations of a 'class
having a common subreg with another' becomeing impossible. Just
doing so explodes our register info to 4+Gb, uncompilable too.
The solution proposed is to define _lo128 RC with contigous 896
VGPRs, but the allocation order of it hiding prohibited registers.
That keeps generated register info a reasonable size (+~50%).
The same is needed to VGPR_16_Lo128 in true16 mode.
In general we could later reuse VGPR_32 with AltOrderSelect, but
we would need to pass there operand type and deal with the AsmParser.
One other consideration is that we can allocate a register leaving
a hole of the whole 128 registers, but a subsequent patch can fix
it, i.e. by the time of the RA we really know estimated register
pressure and can further limit allocation order.
For the short: w/o it we either have spilling when we have VGPRs
available, or outright have 'run out of registers' when we have
a lot of 16-bit registers used, a lot of budget, but we cannot
encode it.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 16 +-
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 6 +-
llvm/lib/Target/AMDGPU/SIInstrFormats.td | 21 +
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 2 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 20 +-
.../Target/AMDGPU/SIShrinkInstructions.cpp | 3 +-
.../GlobalISel/irtranslator-inline-asm.ll | 32 +-
.../regbankcombiner-ignore-copies-crash.mir | 4 +-
.../AMDGPU/branch-relax-indirect-branch.mir | 4 +-
.../AMDGPU/branch-relax-no-terminators.mir | 4 +-
.../coalesce-copy-to-agpr-to-av-registers.mir | 240 ++++++------
.../AMDGPU/coalescer-early-clobber-subreg.mir | 16 +-
llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir | 24 +-
llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir | 4 +-
...class-vgpr-mfma-to-av-with-load-source.mir | 12 +-
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll | 24 +-
...local-stack-alloc-add-references.gfx10.mir | 30 +-
.../local-stack-alloc-add-references.gfx8.mir | 360 +++++++++---------
.../local-stack-alloc-add-references.gfx9.mir | 180 ++++-----
.../machine-scheduler-sink-trivial-remats.mir | 6 +-
.../test/CodeGen/AMDGPU/no-limit-coalesce.mir | 4 +-
...ize-exec-mask-pre-ra-no-fold-exec-copy.mir | 4 +-
...al-regcopy-and-spill-missed-at-regalloc.ll | 24 +-
.../AMDGPU/regalloc-vgpr_lo128-gfx1250.mir | 94 +++++
.../AMDGPU/rename-independent-subregs.mir | 4 +-
.../rewrite-vgpr-mfma-to-agpr-copy-from.mir | 4 +-
...gpr-mfma-to-agpr-subreg-insert-extract.mir | 12 +-
...te-vgpr-mfma-to-agpr-subreg-src2-chain.mir | 36 +-
...ssert-dead-def-subreg-use-other-subreg.mir | 4 +-
...dleMoveUp-subreg-def-across-subreg-def.mir | 16 +-
.../AMDGPU/shrink-vgpr_lo128-gfx1250.mir | 89 +++++
.../CodeGen/AMDGPU/spill-vector-superclass.ll | 4 +-
...ubreg-undef-def-with-other-subreg-defs.mir | 24 +-
.../AMDGPU/gfx11_dasm_vop1_dpp16.txt | 92 ++---
.../AMDGPU/gfx11_dasm_vop1_dpp8.txt | 69 ++--
.../AMDGPU/gfx11_dasm_vop2_dpp16.txt | 12 +-
.../AMDGPU/gfx11_dasm_vop2_dpp8.txt | 9 +-
.../AMDGPU/gfx1250_dasm_vop1_dpp8.txt | 26 +-
.../AMDGPU/gfx12_dasm_vop1_dpp16.txt | 92 ++---
.../AMDGPU/gfx12_dasm_vop1_dpp8.txt | 95 ++---
.../AMDGPU/gfx12_dasm_vop2_dpp16.txt | 12 +-
.../AMDGPU/gfx12_dasm_vop2_dpp8.txt | 9 +-
42 files changed, 998 insertions(+), 745 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 7a91a40e18cde..8430f2e3b4344 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -426,6 +426,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrInline(RCID, type) && !hasModifiers();
}
+ bool isVGPR32_Lo128() const;
+
bool isSCSrcB16() const {
return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16);
}
@@ -2243,7 +2245,19 @@ bool AMDGPUOperand::isLiteralImm(MVT type) const {
}
bool AMDGPUOperand::isRegClass(unsigned RCID) const {
- return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
+ if (!isRegKind() ||
+ !AsmParser->getMRI()->getRegClass(RCID).contains(getReg()))
+ return false;
+ if (RCID == AMDGPU::VGPR_32_Lo128RegClassID ||
+ RCID == AMDGPU::VS_32_Lo128RegClassID)
+ return getReg() <= AMDGPU::VGPR127 || getReg() > AMDGPU::VGPR1023;
+ return true;
+}
+
+bool AMDGPUOperand::isVGPR32_Lo128() const {
+ if (!isRegKind())
+ return false;
+ return getReg() >= AMDGPU::VGPR0 && getReg() <= AMDGPU::VGPR127;
}
bool AMDGPUOperand::isVRegWithInputMods() const {
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index b63d71dc2fde9..55cd800d201db 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -813,7 +813,11 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
OpInfo, STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo));
const MCRegisterClass &RC = MRI.getRegClass(RCID);
auto Reg = mc2PseudoReg(Op.getReg());
- if (!RC.contains(Reg) && !isInlineValue(Reg)) {
+ bool Err = !RC.contains(Reg) && !isInlineValue(Reg);
+ if (!Err && (RCID == AMDGPU::VGPR_32_Lo128RegClassID ||
+ RCID == AMDGPU::VS_32_Lo128RegClassID))
+ Err = Reg >= AMDGPU::VGPR128 && Reg <= AMDGPU::VGPR1023;
+ if (Err) {
bool IsWaveSizeOp = OpInfo.isLookupRegClassByHwMode() &&
(OpInfo.RegClass == AMDGPU::SReg_1 ||
OpInfo.RegClass == AMDGPU::SReg_1_XEXEC);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index de66c472be0ca..cb036b517f2e2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -323,6 +323,12 @@ def CPolBit {
class VOPDstOperand<RegisterClassLike rc> : RegisterOperand<rc, "printVOPDst">;
+def Vgpr32Lo128 : AsmOperandClass {
+ let Name = "Vgpr32Lo128";
+ let PredicateMethod = "isVGPR32_Lo128";
+ let RenderMethod = "addRegOperands";
+}
+
def VOPDstOperand_t16 : VOPDstOperand <VGPR_16> {
let EncoderMethod = "getMachineOpValueT16";
let DecoderMethod = "DecodeVGPR_16RegisterClass";
@@ -333,12 +339,27 @@ def VOPDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> {
let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";
}
+def VOPDstOperand_Vgpr32Lo128 : VOPDstOperand <VGPR_32_Lo128> {
+ let ParserMatchClass = Vgpr32Lo128;
+}
+
// Source-encoded destination operand for instructions like v_swap_b16.
def VOPSrcEncodedDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> {
let EncoderMethod = VSrcT_b16_Lo128.EncoderMethod;
let DecoderMethod = VSrcT_b16_Lo128.DecoderMethod;
}
+
+def VGPROp_16_Lo128 : RegisterOperand<VGPR_16_Lo128> {
+ let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";
+ let EncoderMethod = "getMachineOpValueT16Lo128";
+}
+
+def VGPROp_32_Lo128 : RegisterOperand<VGPR_32_Lo128> {
+ let DecoderMethod = "DecodeVGPR_32RegisterClass";
+ let ParserMatchClass = Vgpr32Lo128;
+}
+
class VINTRPe <bits<2> op> : Enc32 {
bits<8> vdst;
bits<8> vsrc;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 628b972f97086..8738df31a9a56 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1817,7 +1817,7 @@ class getVALUDstForVT_fake16<ValueType VT> {
RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
!if(!eq(VT.Size, 128), VOPDstOperand<VReg_128_AlignTarget>,
!if(!eq(VT.Size, 64), VOPDstOperand<VReg_64_AlignTarget>,
- !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32_Lo128>,
+ !if(!eq(VT.Size, 16), VOPDstOperand_Vgpr32Lo128,
VOPDstS64orS32)))); // else VT == i1
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 272d4b5609dfb..838d31df5bacd 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -632,13 +632,20 @@ def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types
let BaseClassOrder = 32;
}
-// Identical to VGPR_32 except it only contains the low 128 (Lo128) registers.
+// Identical to VGPR_32 except only the low 128 (Lo128) registers in each
+// register bank are allocatable.
def VGPR_32_Lo128 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,
- (add (sequence "VGPR%u", 0, 127))> {
+ (add (sequence "VGPR%u", 0, 895))> {
+ let AltOrders = [(add (sequence "VGPR%u", 0, 127),
+ (sequence "VGPR%u", 256, 383),
+ (sequence "VGPR%u", 512, 639),
+ (sequence "VGPR%u", 768, 895))];
+ let AltOrderSelect = [{ return 1; }];
let AllocationPriority = !add(0, !mul(BaseClassPriority, BaseClassScaleFactor));
let GeneratePressureSet = 0;
let Size = 32;
let Weight = 1;
+ let BaseClassOrder = 33;
}
// Identical to VGPR_32 except it only contains the low 256 (Lo256) registers.
@@ -1487,15 +1494,6 @@ foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "320", "35
def VGPROp_#size#_Align2 : RegisterOperand<!cast<RegisterClassLike>("VReg_"#size#_Align2)>;
}
-def VGPROp_16_Lo128 : RegisterOperand<VGPR_16_Lo128> {
- let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";
- let EncoderMethod = "getMachineOpValueT16Lo128";
-}
-
-def VGPROp_32_Lo128 : RegisterOperand<VGPR_32_Lo128> {
- let DecoderMethod = "DecodeVGPR_32RegisterClass";
-}
-
//===----------------------------------------------------------------------===//
// ASrc_* Operands with an AccVGPR
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 1b78f67e76d07..df8abccf97362 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -157,7 +157,8 @@ bool SIShrinkInstructions::shouldShrinkTrue16(MachineInstr &MI) const {
assert(!Reg.isVirtual() && "Prior checks should ensure we only shrink "
"True16 Instructions post-RA");
if (AMDGPU::VGPR_32RegClass.contains(Reg) &&
- !AMDGPU::VGPR_32_Lo128RegClass.contains(Reg))
+ !llvm::is_contained(
+ AMDGPU::VGPR_32_Lo128RegClass.getRawAllocationOrder(*MF), Reg))
return false;
if (AMDGPU::VGPR_16RegClass.contains(Reg) &&
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
index b290c314f1154..4089e21040b24 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
@@ -66,7 +66,7 @@ define amdgpu_kernel void @asm_simple_agpr_clobber() {
define i32 @asm_vgpr_early_clobber() {
; CHECK-LABEL: name: asm_vgpr_early_clobber
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7; v_mov_b32 $1, 7", 1 /* sideeffect attdialect */, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %8, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %9, !1
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7; v_mov_b32 $1, 7", 1 /* sideeffect attdialect */, 1376267 /* regdef-ec:VGPR_32 */, def early-clobber %8, 1376267 /* regdef-ec:VGPR_32 */, def early-clobber %9, !1
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
@@ -94,7 +94,7 @@ entry:
define i32 @test_single_vgpr_output() nounwind {
; CHECK-LABEL: name: test_single_vgpr_output
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -106,7 +106,7 @@ entry:
define i32 @test_single_sgpr_output_s32() nounwind {
; CHECK-LABEL: name: test_single_sgpr_output_s32
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -119,7 +119,7 @@ entry:
define float @test_multiple_register_outputs_same() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_same
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_mov_b32 $1, 1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %8, 1245194 /* regdef:VGPR_32 */, def %9
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_mov_b32 $1, 1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %8, 1376266 /* regdef:VGPR_32 */, def %9
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
@@ -136,7 +136,7 @@ define float @test_multiple_register_outputs_same() #0 {
define double @test_multiple_register_outputs_mixed() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_mixed
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %8, 2818058 /* regdef:VReg_64 */, def %9
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %8, 2883594 /* regdef:VReg_64 */, def %9
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %9
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
@@ -171,7 +171,7 @@ define amdgpu_kernel void @test_input_vgpr_imm() {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[C]](s32)
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 v0, $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 v0, $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY1]]
; CHECK-NEXT: S_ENDPGM 0
call void asm sideeffect "v_mov_b32 v0, $0", "v"(i32 42)
ret void
@@ -185,7 +185,7 @@ define amdgpu_kernel void @test_input_sgpr_imm() {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[C]](s32)
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 s0, $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 s0, $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[COPY1]]
; CHECK-NEXT: S_ENDPGM 0
call void asm sideeffect "s_mov_b32 s0, $0", "s"(i32 42)
ret void
@@ -212,7 +212,7 @@ define float @test_input_vgpr(i32 %src) nounwind {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
- ; CHECK-NEXT: INLINEASM &"v_add_f32 $0, 1.0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %9, 1245193 /* reguse:VGPR_32 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"v_add_f32 $0, 1.0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %9, 1376265 /* reguse:VGPR_32 */, [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -227,7 +227,7 @@ define i32 @test_memory_constraint(ptr addrspace(3) %a) nounwind {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: INLINEASM &"ds_read_b32 $0, $1", 8 /* mayload attdialect */, 1245194 /* regdef:VGPR_32 */, def %9, 262158 /* mem:m */, [[COPY]](p3)
+ ; CHECK-NEXT: INLINEASM &"ds_read_b32 $0, $1", 8 /* mayload attdialect */, 1376266 /* regdef:VGPR_32 */, def %9, 262158 /* mem:m */, [[COPY]](p3)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -244,7 +244,7 @@ define i32 @test_vgpr_matching_constraint(i32 %a) nounwind {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[AND]](s32)
- ; CHECK-NEXT: INLINEASM &";", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %11, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &";", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %11, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %11
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -256,13 +256,13 @@ define i32 @test_vgpr_matching_constraint(i32 %a) nounwind {
define i32 @test_sgpr_matching_constraint() nounwind {
; CHECK-LABEL: name: test_sgpr_matching_constraint
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 8", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %10
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 8", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: INLINEASM &"s_add_u32 $0, $1, $2", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %12, 1835017 /* reguse:SReg_32 */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"s_add_u32 $0, $1, $2", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %12, 1966089 /* reguse:SReg_32 */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY %12
; CHECK-NEXT: $vgpr0 = COPY [[COPY4]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -285,7 +285,7 @@ define void @test_many_matching_constraints(i32 %a, i32 %b, i32 %c) nounwind {
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: INLINEASM &"; ", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %11, 1245194 /* regdef:VGPR_32 */, def %12, 1245194 /* regdef:VGPR_32 */, def %13, 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3), 2147614729 /* reguse tiedto:$2 */, [[COPY4]](tied-def 7), 2147549193 /* reguse tiedto:$1 */, [[COPY5]](tied-def 5)
+ ; CHECK-NEXT: INLINEASM &"; ", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %11, 1376266 /* regdef:VGPR_32 */, def %12, 1376266 /* regdef:VGPR_32 */, def %13, 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3), 2147614729 /* reguse tiedto:$2 */, [[COPY4]](tied-def 7), 2147549193 /* reguse tiedto:$1 */, [[COPY5]](tied-def 5)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY %11
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY %12
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY %13
@@ -306,10 +306,10 @@ define void @test_many_matching_constraints(i32 %a, i32 %b, i32 %c) nounwind {
define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {
; CHECK-LABEL: name: test_sgpr_to_vgpr_move_matching_constraint
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %10, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %10, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %10
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
index 7ca3869b535e4..65bde1e7d8efb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
@@ -24,7 +24,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %5(s32)
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %5(s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], %5, [[COPY2]]
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
@@ -33,7 +33,7 @@ body: |
%2:vgpr(s32) = COPY %1(s32)
%3:vgpr(s32) = G_FMUL %0, %2
%4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
- INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %5:vgpr_32
+ INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %5:vgpr_32
%6:vgpr(s32) = COPY %4(s32)
%7:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %5(s32), %6(s32)
$vgpr0 = COPY %7(s32)
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
index 34c0159dd3ddb..b1690860178de 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
@@ -68,7 +68,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.7(0x7c000000)
; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1835018 /* regdef:SReg_32 */, def renamable $sgpr4
+ ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1966090 /* regdef:SReg_32 */, def renamable $sgpr4
; CHECK-NEXT: S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
; CHECK-NEXT: S_CBRANCH_SCC0 %bb.3, implicit killed $scc
; CHECK-NEXT: {{ $}}
@@ -149,7 +149,7 @@ body: |
successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
- INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1835018 /* regdef:SReg_32 */, def renamable $sgpr4
+ INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1966090 /* regdef:SReg_32 */, def renamable $sgpr4
S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
S_CBRANCH_SCC1 %bb.2, implicit killed $scc
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
index 4cf92b0127131..d0e51f0394176 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
@@ -69,7 +69,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.7(0x7c000000)
; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1835018 /* regdef:SReg_32 */, def renamable $sgpr4
+ ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1966090 /* regdef:SReg_32 */, def renamable $sgpr4
; CHECK-NEXT: S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
; CHECK-NEXT: S_CBRANCH_SCC0 %bb.3, implicit killed $scc
; CHECK-NEXT: {{ $}}
@@ -151,7 +151,7 @@ body: |
successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
- INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1835018 /* regdef:SReg_32 */, def renamable $sgpr4
+ INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 1966090 /* regdef:SReg_32 */, def renamable $sgpr4
S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
S_CBRANCH_SCC1 %bb.2, implicit killed $scc
diff --git a/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir b/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
index 9e1444d9213e7..c2dba397928e9 100644
--- a/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
@@ -20,13 +20,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -45,13 +45,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0
%2.sub1:areg_64_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -72,7 +72,7 @@ body: |
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub1:areg_96 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2:areg_96 = COPY [[COPY2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY3]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
@@ -80,7 +80,7 @@ body: |
undef %3.sub0:areg_96 = COPY %0
%3.sub1:areg_96 = COPY %1
%3.sub2:areg_96 = COPY %2
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -101,7 +101,7 @@ body: |
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, [[COPY3]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
@@ -109,7 +109,7 @@ body: |
undef %3.sub0:areg_96_align2 = COPY %0
%3.sub1:areg_96_align2 = COPY %1
%3.sub2:areg_96_align2 = COPY %2
- INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -128,13 +128,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_128 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2_sub3:areg_128 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vreg_64 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128 = COPY %0
%2.sub2_sub3:areg_128 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -153,13 +153,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2_sub3:areg_128_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vreg_64 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128_align2 = COPY %0
%2.sub2_sub3:areg_128_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -178,13 +178,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr9
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:sgpr_32 = COPY $sgpr8
%1:sgpr_32 = COPY $sgpr9
undef %2.sub0:areg_64_align2 = COPY %0
%2.sub1:areg_64_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -203,13 +203,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vreg_64 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0
%2.sub1_sub2:areg_96 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -228,13 +228,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vreg_64 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96_align2 = COPY %0
%2.sub1_sub2:areg_96_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -253,13 +253,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:areg_96 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vgpr_32 = COPY $vgpr2
undef %2.sub0_sub1:areg_96 = COPY %0
%2.sub2:areg_96 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -278,13 +278,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vgpr_32 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0
%2.sub2:areg_96_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -302,12 +302,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -326,13 +326,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0
%2.sub1:areg_64_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -350,12 +350,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_96 = COPY %0
%1.sub1:areg_96 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %1
SI_RETURN
...
@@ -373,12 +373,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_96_align2 = COPY %0
%1.sub1:areg_96_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, %1
SI_RETURN
...
@@ -398,14 +398,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_128 = COPY %0
%1.sub1:areg_128 = COPY %0
%1.sub2:areg_128 = COPY %0
%1.sub3:areg_128 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, killed %1
SI_RETURN
...
@@ -425,14 +425,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_128_align2 = COPY %0
%1.sub1:areg_128_align2 = COPY %0
%1.sub2:areg_128_align2 = COPY %0
%1.sub3:areg_128_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %1
SI_RETURN
...
@@ -451,15 +451,15 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %2
- INLINEASM &"; use $0", 0 /* attdialect */, 1245193 /* reguse:VGPR_32 */, killed %0
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 1376265 /* reguse:VGPR_32 */, killed %0
SI_RETURN
...
@@ -477,14 +477,14 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_64 = COPY %0
%1.sub1:areg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %1
- INLINEASM &"; use $0", 0 /* attdialect */, 1245193 /* reguse:VGPR_32 */, killed %0
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 1376265 /* reguse:VGPR_32 */, killed %0
SI_RETURN
...
@@ -503,16 +503,16 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 2818057 /* reguse:VReg_64 */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 2883593 /* reguse:VReg_64 */, [[COPY]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_64 = COPY %0
%1.sub1:areg_64 = COPY %0
undef %2.sub0:vreg_64 = COPY %0
%2.sub1:vreg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %1
- INLINEASM &"; use $0", 0 /* attdialect */, 2818057 /* reguse:VReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 2883593 /* reguse:VReg_64 */, killed %2
SI_RETURN
...
@@ -533,13 +533,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
%0.sub1:vreg_64 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0.sub0
%2.sub1:areg_64 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -558,13 +558,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
%0.sub1:vreg_64 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -585,7 +585,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1:vreg_96 = COPY $vgpr1
@@ -593,7 +593,7 @@ body: |
undef %3.sub0:areg_96 = COPY %0.sub0
%3.sub1:areg_96 = COPY %0.sub1
%3.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -614,7 +614,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1:vreg_96 = COPY $vgpr1
@@ -622,7 +622,7 @@ body: |
undef %3.sub0:areg_96_align2 = COPY %0.sub0
%3.sub1:areg_96_align2 = COPY %0.sub1
%3.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -641,13 +641,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128 = COPY [[COPY]].sub2_sub3
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_128 =COPY $vgpr0_vgpr1
%0.sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128 = COPY %0.sub0_sub1
%2.sub2_sub3:areg_128 = COPY %0.sub2_sub3
- INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -668,13 +668,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_128 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_128 =COPY $vgpr0_vgpr1
%0.sub1:vreg_128 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128_align2 = COPY %0.sub0
%2.sub2_sub3:areg_128_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -693,13 +693,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:sreg_64 = COPY $sgpr9
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:sreg_64 = COPY $sgpr8
%0.sub1:sreg_64 = COPY $sgpr9
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -718,13 +718,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0.sub0
%2.sub1_sub2:areg_96 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -743,13 +743,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96_align2 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96_align2 = COPY %0.sub0
%2.sub1_sub2:areg_96_align2 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -768,13 +768,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96 = COPY %0.sub0_sub1
%2.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -793,13 +793,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0.sub0_sub1
%2.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -817,12 +817,12 @@ body: |
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %2.sub0:areg_64 = COPY %0.sub0
%2.sub1:areg_64 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -841,13 +841,13 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_96 = COPY %0.sub0
%1.sub1:areg_96 = COPY %0.sub0
%1.sub2:areg_96 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %1
SI_RETURN
...
@@ -865,12 +865,12 @@ body: |
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_96_align2 = COPY %0.sub0
%1.sub1:areg_96_align2 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, %1
SI_RETURN
...
@@ -890,14 +890,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_128 = COPY %0.sub0
%1.sub1:areg_128 = COPY %0.sub0
%1.sub2:areg_128 = COPY %0.sub0
%1.sub3:areg_128 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, killed %1
SI_RETURN
...
@@ -917,14 +917,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128_align2 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_128_align2 = COPY %0.sub0
%1.sub1:areg_128_align2 = COPY %0.sub0
%1.sub2:areg_128_align2 = COPY %0.sub0
%1.sub3:areg_128_align2 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %1
SI_RETURN
...
@@ -943,13 +943,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
%0.sub1:vreg_64 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0.sub0
%2.sub1:areg_64 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -968,13 +968,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64_align2 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64_align2 = COPY $vgpr0
%0.sub1:vreg_64_align2 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -995,7 +995,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 = COPY $vgpr0
%0.sub1:vreg_96 = COPY $vgpr1
@@ -1003,7 +1003,7 @@ body: |
undef %3.sub0:areg_96 = COPY %0.sub0
%3.sub1:areg_96 = COPY %0.sub1
%3.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -1024,7 +1024,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96_align2 = COPY $vgpr0
%0.sub1:vreg_96_align2 = COPY $vgpr1
@@ -1032,7 +1032,7 @@ body: |
undef %3.sub0:areg_96_align2 = COPY %0.sub0
%3.sub1:areg_96_align2 = COPY %0.sub1
%3.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -1051,13 +1051,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128 = COPY [[COPY]].sub2_sub3
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_128 = COPY $vgpr0_vgpr1
%0.sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128 = COPY %0.sub0_sub1
%2.sub2_sub3:areg_128 = COPY %0.sub2_sub3
- INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -1076,13 +1076,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:vreg_128_align2 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128_align2 = COPY [[COPY]].sub2_sub3
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_128_align2 = COPY $vgpr0_vgpr1
%0.sub2_sub3:vreg_128_align2 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128_align2 = COPY %0.sub0_sub1
%2.sub2_sub3:areg_128_align2 = COPY %0.sub2_sub3
- INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -1101,13 +1101,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:sreg_64 = COPY $sgpr9
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:sreg_64 = COPY $sgpr8
%0.sub1:sreg_64 = COPY $sgpr9
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1126,13 +1126,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 = COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0.sub0
%2.sub1_sub2:areg_96 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -1150,13 +1150,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 = COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0.sub2
%2.sub1_sub2:areg_96 = COPY %0.sub0_sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -1176,13 +1176,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96_align2 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96_align2 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96_align2 = COPY $vgpr0
%0.sub1_sub2:vreg_96_align2 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96_align2 = COPY %0.sub0
%2.sub1_sub2:areg_96_align2 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1201,13 +1201,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96 = COPY %0.sub0_sub1
%2.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -1226,13 +1226,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96_align2 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96_align2 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96_align2 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0.sub0_sub1
%2.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1251,13 +1251,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0.sub0_sub1
%2.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1274,11 +1274,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_64 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%2:areg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3407881 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -1295,11 +1295,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_64_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr0_vgpr1
%2:areg_64_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1316,11 +1316,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_96 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
%3:areg_96 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 5505033 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6225929 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -1337,11 +1337,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_96_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_96_align2 = COPY $vgpr0_vgpr1_vgpr2
%3:areg_96_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 5832713 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 6553609 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -1358,11 +1358,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_128 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%2:areg_128 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 7929865 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 9633801 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -1379,11 +1379,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_128_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%2:areg_128_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -1400,11 +1400,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_64_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:sreg_64 = COPY $sgpr8_sgpr9
%2:areg_64_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1421,11 +1421,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_96_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
%2:areg_96_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
index 856d1e66fee9d..f90e84f458a83 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
@@ -20,10 +20,10 @@ body: |
; CHECK-LABEL: name: foo1
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %2.sub0, 1245195 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def undef %2.sub0, 1376267 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %0:vgpr_32, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %0:vgpr_32, 1376267 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %0
%2.sub1:vreg_64 = COPY killed %1
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
@@ -41,10 +41,10 @@ body: |
; CHECK-LABEL: name: foo2
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1245195 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1, 1245194 /* regdef:VGPR_32 */, def undef %2.sub0
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1376267 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1, 1376266 /* regdef:VGPR_32 */, def undef %2.sub0
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32, 1245194 /* regdef:VGPR_32 */, def %0:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 1376267 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32, 1376266 /* regdef:VGPR_32 */, def %0:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %0
%2.sub1:vreg_64 = COPY killed %1
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
@@ -62,10 +62,10 @@ body: |
; CHECK-LABEL: name: foo3
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %2.sub0, 1245195 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def undef %2.sub0, 1376267 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %1:vgpr_32, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %1:vgpr_32, 1376267 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %1
%2.sub1:vreg_64 = COPY killed %0
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
@@ -83,10 +83,10 @@ body: |
; CHECK-LABEL: name: foo4
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1245195 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1, 1245194 /* regdef:VGPR_32 */, def undef %2.sub0
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1376267 /* regdef-ec:VGPR_32 */, def undef early-clobber %2.sub1, 1376266 /* regdef:VGPR_32 */, def undef %2.sub0
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32, 1245194 /* regdef:VGPR_32 */, def %1:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 1376267 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32, 1376266 /* regdef:VGPR_32 */, def %1:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %1
%2.sub1:vreg_64 = COPY killed %0
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
diff --git a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
index 98472552d2bf1..a96aa82598fab 100644
--- a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
@@ -370,7 +370,7 @@ body: |
; HAZARD-LABEL: name: inline_sdwa_hazard
; HAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; HAZARD-NEXT: {{ $}}
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
; HAZARD-NEXT: S_NOP 0
; HAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; HAZARD-NEXT: S_ENDPGM 0
@@ -378,10 +378,10 @@ body: |
; NOHAZARD-LABEL: name: inline_sdwa_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
; NOHAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; NOHAZARD-NEXT: S_ENDPGM 0
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
S_ENDPGM 0
...
@@ -397,17 +397,17 @@ body: |
; HAZARD-NEXT: {{ $}}
; HAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; HAZARD-NEXT: S_NOP 0
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
; HAZARD-NEXT: S_ENDPGM 0
;
; NOHAZARD-LABEL: name: sdwa_inline_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
; NOHAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
; NOHAZARD-NEXT: S_ENDPGM 0
renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
S_ENDPGM 0
...
@@ -421,19 +421,19 @@ body: |
; HAZARD-LABEL: name: inline_inline_hazard
; HAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; HAZARD-NEXT: {{ $}}
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
; HAZARD-NEXT: S_NOP 0
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
; HAZARD-NEXT: S_ENDPGM 0
;
; NOHAZARD-LABEL: name: inline_inline_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
; NOHAZARD-NEXT: S_ENDPGM 0
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def $vgpr0, 1245193 /* reguse:VGPR_32 */, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def $vgpr0, 1376265 /* reguse:VGPR_32 */, $vgpr1
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir b/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
index 437b4e8b9b493..cbb2aebdd3f5b 100644
--- a/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
+++ b/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
@@ -1112,11 +1112,11 @@ body: |
; GCN-NEXT: S_WAITCNT 0
; GCN-NEXT: renamable $vgpr2 = V_CVT_SCALEF32_PK_FP4_F16_e64 8, killed $vgpr0, 0, killed $vgpr1, 4, killed $vgpr2, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, killed renamable $vgpr2
+ ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, killed renamable $vgpr2
; GCN-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31
S_WAITCNT 0
renamable $vgpr2 = V_CVT_SCALEF32_PK_FP4_F16_e64 8, killed $vgpr0, 0, killed $vgpr1, 4, killed $vgpr2, 0, implicit $mode, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, killed renamable $vgpr2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, killed renamable $vgpr2
S_SETPC_B64_return undef $sgpr30_sgpr31
...
diff --git a/llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir b/llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
index 382a8d38fd652..97929bdb20f33 100644
--- a/llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
+++ b/llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
@@ -486,7 +486,7 @@ body: |
; CHECK-NEXT: S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55
; CHECK-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
- ; CHECK-NEXT: INLINEASM &"; use $0 ", 1 /* sideeffect attdialect */, 39321609 /* reguse:VReg_512_Align2 */, killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: INLINEASM &"; use $0 ", 1 /* sideeffect attdialect */, 51118089 /* reguse:VReg_512_Align2 */, killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK-NEXT: S_ENDPGM 0
bb.0:
S_NOP 0, implicit-def $agpr0
@@ -516,7 +516,7 @@ body: |
S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47
S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55
S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
- INLINEASM &"; use $0 ", 1 /* sideeffect attdialect */, 39321609 /* reguse:VReg_512_Align2 */, %0:vreg_512_align2
+ INLINEASM &"; use $0 ", 1 /* sideeffect attdialect */, 51118089 /* reguse:VReg_512_Align2 */, %0:vreg_512_align2
S_ENDPGM 0
...
@@ -1368,7 +1368,7 @@ body: |
; CHECK-NEXT: renamable $vgpr0_vgpr1 = GLOBAL_LOAD_DWORDX2 undef renamable $vgpr0_vgpr1, 0, 0, implicit $exec :: (load (s64), addrspace 1)
; CHECK-NEXT: early-clobber renamable $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33 = V_MFMA_F32_32X32X8F16_vgprcd_e64 $vgpr16_vgpr17, $vgpr16_vgpr17, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: early-clobber renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = V_MFMA_F32_32X32X8F16_vgprcd_e64 $vgpr16_vgpr17, $vgpr16_vgpr17, $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 39321609 /* reguse:VReg_512_Align2 */, killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 51118089 /* reguse:VReg_512_Align2 */, killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
@@ -1408,7 +1408,7 @@ body: |
undef %2.sub0_sub1:vreg_512_align2 = GLOBAL_LOAD_DWORDX2 undef %3:vreg_64_align2, 0, 0, implicit $exec :: (load (s64), addrspace 1)
early-clobber %0:vreg_512_align2 = V_MFMA_F32_32X32X8F16_vgprcd_e64 %1, %1, %2, 0, 0, 0, implicit $mode, implicit $exec
early-clobber %4:vreg_512_align2 = V_MFMA_F32_32X32X8F16_vgprcd_e64 %1, %1, %0, 0, 0, 0, implicit $mode, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 39321609 /* reguse:VReg_512_Align2 */, %4
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 51118089 /* reguse:VReg_512_Align2 */, %4
S_CBRANCH_VCCNZ %bb.1, implicit $vcc
S_BRANCH %bb.2
@@ -1726,7 +1726,7 @@ body: |
; CHECK-NEXT: renamable $vgpr0_vgpr1 = GLOBAL_LOAD_DWORDX2 undef renamable $vgpr0_vgpr1, 0, 0, implicit $exec :: (load (s64), addrspace 1)
; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 $vgpr16_vgpr17, $vgpr16_vgpr17, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: early-clobber renamable $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33 = V_MFMA_F32_32X32X8F16_vgprcd_e64 $vgpr16_vgpr17, $vgpr16_vgpr17, killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 39321609 /* reguse:VReg_512_Align2 */, renamable $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 51118089 /* reguse:VReg_512_Align2 */, renamable $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33
; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
@@ -1763,7 +1763,7 @@ body: |
undef %0.sub0_sub1:vreg_512_align2 = GLOBAL_LOAD_DWORDX2 undef %3:vreg_64_align2, 0, 0, implicit $exec :: (load (s64), addrspace 1)
%0:vreg_512_align2 = V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %1, %1, %0, 0, 0, 0, implicit $mode, implicit $exec
%4:vreg_512_align2 = V_MFMA_F32_32X32X8F16_vgprcd_e64 %1, %1, %0, 0, 0, 0, implicit $mode, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 39321609 /* reguse:VReg_512_Align2 */, %4
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 51118089 /* reguse:VReg_512_Align2 */, %4
S_CBRANCH_VCCNZ %bb.1, implicit $vcc
S_BRANCH %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
index 9e1d59064cb5e..f8111260ffdc4 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
@@ -8,16 +8,16 @@
define amdgpu_kernel void @s_input_output_i128() {
; GFX908-LABEL: name: s_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 9764874 /* regdef:SGPR_128 */, def %13
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 11075594 /* regdef:SGPR_128 */, def %13
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %13
- ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 9764873 /* reguse:SGPR_128 */, [[COPY]]
+ ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 11075593 /* reguse:SGPR_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: s_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 9764874 /* regdef:SGPR_128 */, def %11
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 11075594 /* regdef:SGPR_128 */, def %11
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %11
- ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 9764873 /* reguse:SGPR_128 */, [[COPY]]
+ ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 11075593 /* reguse:SGPR_128 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = tail call i128 asm sideeffect "; def $0", "=s"()
call void asm sideeffect "; use $0", "s"(i128 %val)
@@ -27,16 +27,16 @@ define amdgpu_kernel void @s_input_output_i128() {
define amdgpu_kernel void @v_input_output_i128() {
; GFX908-LABEL: name: v_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7012362 /* regdef:VReg_128 */, def %13
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7733258 /* regdef:VReg_128 */, def %13
; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %13
- ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7012361 /* reguse:VReg_128 */, [[COPY]]
+ ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7733257 /* reguse:VReg_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: v_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7340042 /* regdef:VReg_128_Align2 */, def %11
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8585226 /* regdef:VReg_128_Align2 */, def %11
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %11
- ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7340041 /* reguse:VReg_128_Align2 */, [[COPY]]
+ ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8585225 /* reguse:VReg_128_Align2 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = tail call i128 asm sideeffect "; def $0", "=v"()
call void asm sideeffect "; use $0", "v"(i128 %val)
@@ -47,16 +47,16 @@ define amdgpu_kernel void @a_input_output_i128() {
; GFX908-LABEL: name: a_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7929866 /* regdef:AReg_128 */, def %13
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 9633802 /* regdef:AReg_128 */, def %13
; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY %13
- ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7929865 /* reguse:AReg_128 */, [[COPY]]
+ ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 9633801 /* reguse:AReg_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: a_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8650762 /* regdef:AReg_128_Align2 */, def %11
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10092554 /* regdef:AReg_128_Align2 */, def %11
; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %11
- ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY]]
+ ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = call i128 asm sideeffect "; def $0", "=a"()
call void asm sideeffect "; use $0", "a"(i128 %val)
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
index 8ea9ec397fe06..62ab4414f806f 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
@@ -18,21 +18,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], 256, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 256, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 512, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, 256, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 %stack.0, 512, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -53,27 +53,27 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 256, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], -156, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 256, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 512, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 100, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 256, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 512, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
%2:vgpr_32 = V_ADD_U32_e64 %stack.0, 100, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %2
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
index 71c47c80ae357..63aa3d802f6c4 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
@@ -21,9 +21,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_CO_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -31,9 +31,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -41,10 +41,10 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -52,9 +52,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -62,15 +62,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -88,42 +88,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX803: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX900: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX942: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX10: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX12: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1, implicit $vcc
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1, implicit $vcc
SI_RETURN
...
@@ -144,9 +144,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_CO_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -154,9 +154,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -164,10 +164,10 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -175,9 +175,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -185,15 +185,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_CO_U32_e32 8, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 16, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -214,9 +214,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_CO_U32_e64_]], 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -224,9 +224,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -234,9 +234,9 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[S_ADD_I32_]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -244,9 +244,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -254,14 +254,14 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[S_ADD_I32_]], 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32, dead %2:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -279,42 +279,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX803: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX900: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX900-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX942: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX942-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX10: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX10-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX12: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX12-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
%0:vgpr_32, %2:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32, %3:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN implicit %2
...
@@ -332,42 +332,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX803: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX900: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX942: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX12: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %0
%1:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %1
SI_RETURN
...
@@ -385,42 +385,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX803: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX900: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX942: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX12: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %0
%1:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %1
SI_RETURN
...
@@ -443,9 +443,9 @@ body: |
; GFX803-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX803-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX803-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -454,9 +454,9 @@ body: |
; GFX900-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX900-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX900-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -465,9 +465,9 @@ body: |
; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -476,9 +476,9 @@ body: |
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX10-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -487,17 +487,17 @@ body: |
; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = COPY $sgpr4
%1:sreg_32 = COPY $sgpr5
%2:sreg_32 = S_ADD_I32 %0, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %2
%3:sreg_32 = S_ADD_I32 %1, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %3
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %3
SI_RETURN
...
@@ -520,9 +520,9 @@ body: |
; GFX803-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX803-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX803-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -531,9 +531,9 @@ body: |
; GFX900-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX900-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX900-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -542,9 +542,9 @@ body: |
; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -553,9 +553,9 @@ body: |
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX10-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -564,17 +564,17 @@ body: |
; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = COPY $sgpr4
%1:sreg_32 = COPY $sgpr5
%2:sreg_32 = S_ADD_I32 %stack.0, %0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %2
%3:sreg_32 = S_ADD_I32 %stack.0, %1, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %3
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %3
SI_RETURN
...
@@ -592,48 +592,48 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX803: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: S_NOP 0, implicit $scc
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN implicit $scc
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX900: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: S_NOP 0, implicit $scc
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN implicit $scc
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX942: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: S_NOP 0, implicit $scc
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN implicit $scc
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: S_NOP 0, implicit $scc
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN implicit $scc
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX12: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: S_NOP 0, implicit $scc
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN implicit $scc
%0:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %0
S_NOP 0, implicit $scc
%1:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1966089 /* reguse:SReg_32 */, %1
SI_RETURN implicit $scc
...
@@ -656,9 +656,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -667,9 +667,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -678,9 +678,9 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -689,9 +689,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -700,15 +700,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -731,9 +731,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -742,9 +742,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -753,9 +753,9 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -764,9 +764,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -775,15 +775,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_CO_U32_e32 %stack.0, %vgpr_offset, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 %stack.0, %vgpr_offset, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -805,9 +805,9 @@ body: |
; GFX803-NEXT: {{ $}}
; GFX803-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -815,9 +815,9 @@ body: |
; GFX900-NEXT: {{ $}}
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -825,9 +825,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -836,9 +836,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -848,16 +848,16 @@ body: |
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[COPY]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -880,9 +880,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -891,9 +891,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -903,10 +903,10 @@ body: |
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[COPY]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[COPY1]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -915,9 +915,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -926,15 +926,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[S_MOV_B32_]], 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[S_MOV_B32_]], 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32, dead %2:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -957,9 +957,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -968,9 +968,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -980,10 +980,10 @@ body: |
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY %sgpr_offset
; GFX942-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[COPY]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY %sgpr_offset
; GFX942-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[COPY1]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -992,9 +992,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -1003,15 +1003,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32, dead %2:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
index f0868ffeeb7c5..a832d855aa0e0 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
@@ -20,16 +20,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
; GFX942: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 512, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
@@ -37,21 +37,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
; GFX12: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 512, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e32 256, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 512, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -72,16 +72,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
; GFX942: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 16, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
@@ -89,21 +89,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
; GFX12: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 16, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e32 8, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 16, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -124,16 +124,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
; GFX942: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
@@ -141,21 +141,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -178,9 +178,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets
@@ -188,9 +188,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets
@@ -199,9 +199,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets
@@ -209,15 +209,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -240,9 +240,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets_commute
@@ -250,9 +250,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets_commute
@@ -261,9 +261,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets_commute
@@ -271,15 +271,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -301,9 +301,9 @@ body: |
; GFX900-NEXT: {{ $}}
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__sgpr_offsets
@@ -311,9 +311,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__sgpr_offsets
@@ -322,9 +322,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__sgpr_offsets
@@ -332,15 +332,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -363,9 +363,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets
@@ -373,9 +373,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets
@@ -384,9 +384,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets
@@ -394,15 +394,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -425,9 +425,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets_commute
@@ -435,9 +435,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets_commute
@@ -446,9 +446,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets_commute
@@ -456,15 +456,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -486,16 +486,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 1, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
; GFX942: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 1, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 1, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
@@ -503,21 +503,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 1, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 1, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 1, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, /*clamp*/1, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 16, %stack.0, /*clamp*/1, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %1
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
index 8d24f6ba66968..bf3f55a7ec6e2 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
@@ -9571,7 +9571,7 @@ body: |
; GFX908-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
- ; GFX908-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %22, 1245193 /* reguse:VGPR_32 */, [[V_CVT_I32_F64_e32_4]]
+ ; GFX908-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %22, 1376265 /* reguse:VGPR_32 */, [[V_CVT_I32_F64_e32_4]]
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.2(0x80000000)
@@ -9622,7 +9622,7 @@ body: |
; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
- ; GFX908-GCNTRACKERS-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %22, 1245193 /* reguse:VGPR_32 */, [[V_CVT_I32_F64_e32_4]]
+ ; GFX908-GCNTRACKERS-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %22, 1376265 /* reguse:VGPR_32 */, [[V_CVT_I32_F64_e32_4]]
; GFX908-GCNTRACKERS-NEXT: {{ $}}
; GFX908-GCNTRACKERS-NEXT: bb.1:
; GFX908-GCNTRACKERS-NEXT: successors: %bb.2(0x80000000)
@@ -9671,7 +9671,7 @@ body: |
%19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0
%20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
%21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %22:vgpr_32, 1245193 /* reguse:VGPR_32 */, %4
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1376266 /* regdef:VGPR_32 */, def %22:vgpr_32, 1376265 /* reguse:VGPR_32 */, %4
%23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode
bb.1:
diff --git a/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
index 934a536edb726..254a84475ca88 100644
--- a/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
+++ b/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
@@ -15,7 +15,7 @@ body: |
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub1:sgpr_64 = COPY $sgpr17
; CHECK-NEXT: [[COPY:%[0-9]+]].sub0:sgpr_64 = COPY $sgpr16
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: INLINEASM &"; def $0", 0 /* attdialect */, 2818058 /* regdef:VReg_64 */, def undef %5.sub0_sub1
+ ; CHECK-NEXT: INLINEASM &"; def $0", 0 /* attdialect */, 2883594 /* regdef:VReg_64 */, def undef %5.sub0_sub1
; CHECK-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], %5.sub1_sub2_sub3_sub4, [[COPY]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:sgpr_32 = COPY killed $sgpr17
@@ -23,7 +23,7 @@ body: |
undef %2.sub0:sgpr_64 = COPY killed %1
%2.sub1:sgpr_64 = COPY killed %0
%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- INLINEASM &"; def $0", 0 /* attdialect */, 2818058 /* regdef:VReg_64 */, def %4:vreg_64
+ INLINEASM &"; def $0", 0 /* attdialect */, 2883594 /* regdef:VReg_64 */, def %4:vreg_64
undef %5.sub0:vreg_128 = COPY killed %4.sub1
GLOBAL_STORE_DWORDX4_SADDR killed %3, killed %5, killed %2, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
index 8cdc0833cb0be..643bfa3eddb7a 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
@@ -15,7 +15,7 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $exec
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 4653065 /* reguse:SGPR_64 */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 4915209 /* reguse:SGPR_64 */, [[COPY]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: SI_RETURN
@@ -23,7 +23,7 @@ body: |
successors: %bb.1(0x80000000)
%0:sgpr_64 = COPY $exec
- INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 4653065 /* reguse:SGPR_64 */, %0
+ INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 4915209 /* reguse:SGPR_64 */, %0
bb.1:
SI_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
index 6381db7b69cd4..97f9fb0dfd4b0 100644
--- a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
@@ -11,10 +11,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; REGALLOC-GFX908: bb.0 (%ir-block.0):
; REGALLOC-GFX908-NEXT: liveins: $sgpr4_sgpr5
; REGALLOC-GFX908-NEXT: {{ $}}
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1638409 /* reguse:AGPR_32 */, undef %6:agpr_32
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7012362 /* regdef:VReg_128 */, def %25
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:AGPR_32 */, undef %6:agpr_32
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7733258 /* regdef:VReg_128 */, def %25
; REGALLOC-GFX908-NEXT: [[COPY:%[0-9]+]]:av_128 = COPY %25
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 2818058 /* regdef:VReg_64 */, def %27
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 2883594 /* regdef:VReg_64 */, def %27
; REGALLOC-GFX908-NEXT: SI_SPILL_AV64_SAVE %27, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, align 4, addrspace 5)
; REGALLOC-GFX908-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[COPY]]
; REGALLOC-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef %15:vreg_64, [[COPY1]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
@@ -36,10 +36,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; PEI-GFX908-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
; PEI-GFX908-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
; PEI-GFX908-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
- ; PEI-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1638409 /* reguse:AGPR_32 */, undef renamable $agpr0
- ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7012362 /* regdef:VReg_128 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
+ ; PEI-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:AGPR_32 */, undef renamable $agpr0
+ ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7733258 /* regdef:VReg_128 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
; PEI-GFX908-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
- ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 2818058 /* regdef:VReg_64 */, def renamable $vgpr0_vgpr1
+ ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 2883594 /* regdef:VReg_64 */, def renamable $vgpr0_vgpr1
; PEI-GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
; PEI-GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1
; PEI-GFX908-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = COPY killed renamable $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -60,10 +60,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; REGALLOC-GFX90A: bb.0 (%ir-block.0):
; REGALLOC-GFX90A-NEXT: liveins: $sgpr4_sgpr5
; REGALLOC-GFX90A-NEXT: {{ $}}
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1638409 /* reguse:AGPR_32 */, undef %6:agpr_32
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7340042 /* regdef:VReg_128_Align2 */, def %23
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:AGPR_32 */, undef %6:agpr_32
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8585226 /* regdef:VReg_128_Align2 */, def %23
; REGALLOC-GFX90A-NEXT: [[COPY:%[0-9]+]]:av_128_align2 = COPY %23
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3080202 /* regdef:VReg_64_Align2 */, def %21
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3604490 /* regdef:VReg_64_Align2 */, def %21
; REGALLOC-GFX90A-NEXT: [[COPY1:%[0-9]+]]:av_64_align2 = COPY %21
; REGALLOC-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef %15:vreg_64_align2, [[COPY]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; REGALLOC-GFX90A-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
@@ -79,10 +79,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; PEI-GFX90A: bb.0 (%ir-block.0):
; PEI-GFX90A-NEXT: liveins: $sgpr4_sgpr5
; PEI-GFX90A-NEXT: {{ $}}
- ; PEI-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1638409 /* reguse:AGPR_32 */, undef renamable $agpr0
- ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7340042 /* regdef:VReg_128_Align2 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
+ ; PEI-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:AGPR_32 */, undef renamable $agpr0
+ ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8585226 /* regdef:VReg_128_Align2 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
; PEI-GFX90A-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
- ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3080202 /* regdef:VReg_64_Align2 */, def renamable $vgpr2_vgpr3
+ ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3604490 /* regdef:VReg_64_Align2 */, def renamable $vgpr2_vgpr3
; PEI-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $agpr0_agpr1_agpr2_agpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; PEI-GFX90A-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
; PEI-GFX90A-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
new file mode 100644
index 0000000000000..ba0bfadb248c1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
@@ -0,0 +1,94 @@
+# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s | FileCheck --check-prefixes=GCN,GFX11 %s
+# RUN: not llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=greedy,0 -stop-after=virtregrewriter,2 -o - %s | FileCheck --check-prefixes=GCN,GFX1250 %s
+
+--- |
+ define amdgpu_kernel void @rcp_f16_above_128_vregs() #0 { ret void }
+ define amdgpu_kernel void @rcp_f16_above_256_vregs() #0 { ret void }
+ define amdgpu_kernel void @rcp_f16_above_512_vregs() #0 { ret void }
+ define amdgpu_kernel void @rcp_f16_above_768_vregs() #0 { ret void }
+
+ attributes #0 = { "amdgpu-flat-work-group-size"="128,128" "amdgpu-waves-per-eu"="1" }
+...
+
+# GCN-LABEL: name: rcp_f16_above_128_vregs
+
+# GFX11: $vgpr0 = IMPLICIT_DEF
+# GFX11: $vgpr0 = V_RCP_F16_fake16_e32 undef $vgpr0
+
+# Use first free VGPR from the second bank:
+# GFX1250: $vgpr256 = IMPLICIT_DEF
+# GFX1250: $vgpr256 = V_RCP_F16_fake16_e32 killed $vgpr256
+---
+name: rcp_f16_above_128_vregs
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; Occupy all low 128 VGPRs:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127
+
+ %0:vgpr_32_lo128 = IMPLICIT_DEF
+ %1:vgpr_32_lo128 = V_RCP_F16_fake16_e32 killed %0, implicit $mode, implicit $exec
+
+ S_ENDPGM 0, implicit %1, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127
+...
+
+# GCN-LABEL: name: rcp_f16_above_256_vregs
+
+# GFX11: $vgpr0 = IMPLICIT_DEF
+# GFX11: $vgpr0 = V_RCP_F16_fake16_e32 undef $vgpr0
+
+# Use first free VGPR from the third bank:
+# GFX1250: $vgpr512 = IMPLICIT_DEF
+# GFX1250: $vgpr512 = V_RCP_F16_fake16_e32 killed $vgpr512
+---
+name: rcp_f16_above_256_vregs
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263_vgpr264_vgpr265_vgpr266_vgpr267_vgpr268_vgpr269_vgpr270_vgpr271, $vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277_vgpr278_vgpr279_vgpr280_vgpr281_vgpr282_vgpr283_vgpr284_vgpr285_vgpr286_vgpr287, $vgpr288_vgpr289_vgpr290_vgpr291_vgpr292_vgpr293_vgpr294_vgpr295_vgpr296_vgpr297_vgpr298_vgpr299_vgpr300_vgpr301_vgpr302_vgpr303, $vgpr304_vgpr305_vgpr306_vgpr307_vgpr308_vgpr309_vgpr310_vgpr311_vgpr312_vgpr313_vgpr314_vgpr315_vgpr316_vgpr317_vgpr318_vgpr319, $vgpr320_vgpr321_vgpr322_vgpr323_vgpr324_vgpr325_vgpr326_vgpr327_vgpr328_vgpr329_vgpr330_vgpr331_vgpr332_vgpr333_vgpr334_vgpr335, $vgpr336_vgpr337_vgpr338_vgpr339_vgpr340_vgpr341_vgpr342_vgpr343_vgpr344_vgpr345_vgpr346_vgpr347_vgpr348_vgpr349_vgpr350_vgpr351, $vgpr352_vgpr353_vgpr354_vgpr355_vgpr356_vgpr357_vgpr358_vgpr359_vgpr360_vgpr361_vgpr362_vgpr363_vgpr364_vgpr365_vgpr366_vgpr367, $vgpr368_vgpr369_vgpr370_vgpr371_vgpr372_vgpr373_vgpr374_vgpr375_vgpr376_vgpr377_vgpr378_vgpr379_vgpr380_vgpr381_vgpr382_vgpr383
+
+ %0:vgpr_32_lo128 = IMPLICIT_DEF
+ %1:vgpr_32_lo128 = V_RCP_F16_fake16_e32 killed %0, implicit $mode, implicit $exec
+
+ S_ENDPGM 0, implicit %1, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263_vgpr264_vgpr265_vgpr266_vgpr267_vgpr268_vgpr269_vgpr270_vgpr271, implicit $vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277_vgpr278_vgpr279_vgpr280_vgpr281_vgpr282_vgpr283_vgpr284_vgpr285_vgpr286_vgpr287, implicit $vgpr288_vgpr289_vgpr290_vgpr291_vgpr292_vgpr293_vgpr294_vgpr295_vgpr296_vgpr297_vgpr298_vgpr299_vgpr300_vgpr301_vgpr302_vgpr303, implicit $vgpr304_vgpr305_vgpr306_vgpr307_vgpr308_vgpr309_vgpr310_vgpr311_vgpr312_vgpr313_vgpr314_vgpr315_vgpr316_vgpr317_vgpr318_vgpr319, implicit $vgpr320_vgpr321_vgpr322_vgpr323_vgpr324_vgpr325_vgpr326_vgpr327_vgpr328_vgpr329_vgpr330_vgpr331_vgpr332_vgpr333_vgpr334_vgpr335, implicit $vgpr336_vgpr337_vgpr338_vgpr339_vgpr340_vgpr341_vgpr342_vgpr343_vgpr344_vgpr345_vgpr346_vgpr347_vgpr348_vgpr349_vgpr350_vgpr351, implicit $vgpr352_vgpr353_vgpr354_vgpr355_vgpr356_vgpr357_vgpr358_vgpr359_vgpr360_vgpr361_vgpr362_vgpr363_vgpr364_vgpr365_vgpr366_vgpr367, implicit $vgpr368_vgpr369_vgpr370_vgpr371_vgpr372_vgpr373_vgpr374_vgpr375_vgpr376_vgpr377_vgpr378_vgpr379_vgpr380_vgpr381_vgpr382_vgpr383
+...
+
+# GCN-LABEL: name: rcp_f16_above_512_vregs
+
+# GFX11: $vgpr0 = IMPLICIT_DEF
+# GFX11: $vgpr0 = V_RCP_F16_fake16_e32 undef $vgpr0
+
+# Use first free VGPR from the third bank:
+# GFX1250: $vgpr768 = IMPLICIT_DEF
+# GFX1250: $vgpr768 = V_RCP_F16_fake16_e32 killed $vgpr768
+---
+name: rcp_f16_above_512_vregs
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263_vgpr264_vgpr265_vgpr266_vgpr267_vgpr268_vgpr269_vgpr270_vgpr271, $vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277_vgpr278_vgpr279_vgpr280_vgpr281_vgpr282_vgpr283_vgpr284_vgpr285_vgpr286_vgpr287, $vgpr288_vgpr289_vgpr290_vgpr291_vgpr292_vgpr293_vgpr294_vgpr295_vgpr296_vgpr297_vgpr298_vgpr299_vgpr300_vgpr301_vgpr302_vgpr303, $vgpr304_vgpr305_vgpr306_vgpr307_vgpr308_vgpr309_vgpr310_vgpr311_vgpr312_vgpr313_vgpr314_vgpr315_vgpr316_vgpr317_vgpr318_vgpr319, $vgpr320_vgpr321_vgpr322_vgpr323_vgpr324_vgpr325_vgpr326_vgpr327_vgpr328_vgpr329_vgpr330_vgpr331_vgpr332_vgpr333_vgpr334_vgpr335, $vgpr336_vgpr337_vgpr338_vgpr339_vgpr340_vgpr341_vgpr342_vgpr343_vgpr344_vgpr345_vgpr346_vgpr347_vgpr348_vgpr349_vgpr350_vgpr351, $vgpr352_vgpr353_vgpr354_vgpr355_vgpr356_vgpr357_vgpr358_vgpr359_vgpr360_vgpr361_vgpr362_vgpr363_vgpr364_vgpr365_vgpr366_vgpr367, $vgpr368_vgpr369_vgpr370_vgpr371_vgpr372_vgpr373_vgpr374_vgpr375_vgpr376_vgpr377_vgpr378_vgpr379_vgpr380_vgpr381_vgpr382_vgpr383, $vgpr512_vgpr513_vgpr514_vgpr515_vgpr516_vgpr517_vgpr518_vgpr519_vgpr520_vgpr521_vgpr522_vgpr523_vgpr524_vgpr525_vgpr526_vgpr527, $vgpr528_vgpr529_vgpr530_vgpr531_vgpr532_vgpr533_vgpr534_vgpr535_vgpr536_vgpr537_vgpr538_vgpr539_vgpr540_vgpr541_vgpr542_vgpr543, $vgpr544_vgpr545_vgpr546_vgpr547_vgpr548_vgpr549_vgpr550_vgpr551_vgpr552_vgpr553_vgpr554_vgpr555_vgpr556_vgpr557_vgpr558_vgpr559, $vgpr560_vgpr561_vgpr562_vgpr563_vgpr564_vgpr565_vgpr566_vgpr567_vgpr568_vgpr569_vgpr570_vgpr571_vgpr572_vgpr573_vgpr574_vgpr575, $vgpr576_vgpr577_vgpr578_vgpr579_vgpr580_vgpr581_vgpr582_vgpr583_vgpr584_vgpr585_vgpr586_vgpr587_vgpr588_vgpr589_vgpr590_vgpr591, $vgpr592_vgpr593_vgpr594_vgpr595_vgpr596_vgpr597_vgpr598_vgpr599_vgpr600_vgpr601_vgpr602_vgpr603_vgpr604_vgpr605_vgpr606_vgpr607, $vgpr608_vgpr609_vgpr610_vgpr611_vgpr612_vgpr613_vgpr614_vgpr615_vgpr616_vgpr617_vgpr618_vgpr619_vgpr620_vgpr621_vgpr622_vgpr623, $vgpr624_vgpr625_vgpr626_vgpr627_vgpr628_vgpr629_vgpr630_vgpr631_vgpr632_vgpr633_vgpr634_vgpr635_vgpr636_vgpr637_vgpr638_vgpr639
+
+ %0:vgpr_32_lo128 = IMPLICIT_DEF
+ %1:vgpr_32_lo128 = V_RCP_F16_fake16_e32 killed %0, implicit $mode, implicit $exec
+
+ S_ENDPGM 0, implicit %1, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263_vgpr264_vgpr265_vgpr266_vgpr267_vgpr268_vgpr269_vgpr270_vgpr271, implicit $vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277_vgpr278_vgpr279_vgpr280_vgpr281_vgpr282_vgpr283_vgpr284_vgpr285_vgpr286_vgpr287, implicit $vgpr288_vgpr289_vgpr290_vgpr291_vgpr292_vgpr293_vgpr294_vgpr295_vgpr296_vgpr297_vgpr298_vgpr299_vgpr300_vgpr301_vgpr302_vgpr303, implicit $vgpr304_vgpr305_vgpr306_vgpr307_vgpr308_vgpr309_vgpr310_vgpr311_vgpr312_vgpr313_vgpr314_vgpr315_vgpr316_vgpr317_vgpr318_vgpr319, implicit $vgpr320_vgpr321_vgpr322_vgpr323_vgpr324_vgpr325_vgpr326_vgpr327_vgpr328_vgpr329_vgpr330_vgpr331_vgpr332_vgpr333_vgpr334_vgpr335, implicit $vgpr336_vgpr337_vgpr338_vgpr339_vgpr340_vgpr341_vgpr342_vgpr343_vgpr344_vgpr345_vgpr346_vgpr347_vgpr348_vgpr349_vgpr350_vgpr351, implicit $vgpr352_vgpr353_vgpr354_vgpr355_vgpr356_vgpr357_vgpr358_vgpr359_vgpr360_vgpr361_vgpr362_vgpr363_vgpr364_vgpr365_vgpr366_vgpr367, implicit $vgpr368_vgpr369_vgpr370_vgpr371_vgpr372_vgpr373_vgpr374_vgpr375_vgpr376_vgpr377_vgpr378_vgpr379_vgpr380_vgpr381_vgpr382_vgpr383, implicit $vgpr512_vgpr513_vgpr514_vgpr515_vgpr516_vgpr517_vgpr518_vgpr519_vgpr520_vgpr521_vgpr522_vgpr523_vgpr524_vgpr525_vgpr526_vgpr527, implicit $vgpr528_vgpr529_vgpr530_vgpr531_vgpr532_vgpr533_vgpr534_vgpr535_vgpr536_vgpr537_vgpr538_vgpr539_vgpr540_vgpr541_vgpr542_vgpr543, implicit $vgpr544_vgpr545_vgpr546_vgpr547_vgpr548_vgpr549_vgpr550_vgpr551_vgpr552_vgpr553_vgpr554_vgpr555_vgpr556_vgpr557_vgpr558_vgpr559, implicit $vgpr560_vgpr561_vgpr562_vgpr563_vgpr564_vgpr565_vgpr566_vgpr567_vgpr568_vgpr569_vgpr570_vgpr571_vgpr572_vgpr573_vgpr574_vgpr575, implicit $vgpr576_vgpr577_vgpr578_vgpr579_vgpr580_vgpr581_vgpr582_vgpr583_vgpr584_vgpr585_vgpr586_vgpr587_vgpr588_vgpr589_vgpr590_vgpr591, implicit $vgpr592_vgpr593_vgpr594_vgpr595_vgpr596_vgpr597_vgpr598_vgpr599_vgpr600_vgpr601_vgpr602_vgpr603_vgpr604_vgpr605_vgpr606_vgpr607, implicit $vgpr608_vgpr609_vgpr610_vgpr611_vgpr612_vgpr613_vgpr614_vgpr615_vgpr616_vgpr617_vgpr618_vgpr619_vgpr620_vgpr621_vgpr622_vgpr623, implicit $vgpr624_vgpr625_vgpr626_vgpr627_vgpr628_vgpr629_vgpr630_vgpr631_vgpr632_vgpr633_vgpr634_vgpr635_vgpr636_vgpr637_vgpr638_vgpr639
+...
+
+# GCN-LABEL: name: rcp_f16_above_768_vregs
+
+# GCN: $vgpr0 = IMPLICIT_DEF
+# GCN: $vgpr0 = V_RCP_F16_fake16_e32 undef $vgpr0
+
+# No free _lo128 registers left
+---
+name: rcp_f16_above_768_vregs
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263_vgpr264_vgpr265_vgpr266_vgpr267_vgpr268_vgpr269_vgpr270_vgpr271, $vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277_vgpr278_vgpr279_vgpr280_vgpr281_vgpr282_vgpr283_vgpr284_vgpr285_vgpr286_vgpr287, $vgpr288_vgpr289_vgpr290_vgpr291_vgpr292_vgpr293_vgpr294_vgpr295_vgpr296_vgpr297_vgpr298_vgpr299_vgpr300_vgpr301_vgpr302_vgpr303, $vgpr304_vgpr305_vgpr306_vgpr307_vgpr308_vgpr309_vgpr310_vgpr311_vgpr312_vgpr313_vgpr314_vgpr315_vgpr316_vgpr317_vgpr318_vgpr319, $vgpr320_vgpr321_vgpr322_vgpr323_vgpr324_vgpr325_vgpr326_vgpr327_vgpr328_vgpr329_vgpr330_vgpr331_vgpr332_vgpr333_vgpr334_vgpr335, $vgpr336_vgpr337_vgpr338_vgpr339_vgpr340_vgpr341_vgpr342_vgpr343_vgpr344_vgpr345_vgpr346_vgpr347_vgpr348_vgpr349_vgpr350_vgpr351, $vgpr352_vgpr353_vgpr354_vgpr355_vgpr356_vgpr357_vgpr358_vgpr359_vgpr360_vgpr361_vgpr362_vgpr363_vgpr364_vgpr365_vgpr366_vgpr367, $vgpr368_vgpr369_vgpr370_vgpr371_vgpr372_vgpr373_vgpr374_vgpr375_vgpr376_vgpr377_vgpr378_vgpr379_vgpr380_vgpr381_vgpr382_vgpr383, $vgpr512_vgpr513_vgpr514_vgpr515_vgpr516_vgpr517_vgpr518_vgpr519_vgpr520_vgpr521_vgpr522_vgpr523_vgpr524_vgpr525_vgpr526_vgpr527, $vgpr528_vgpr529_vgpr530_vgpr531_vgpr532_vgpr533_vgpr534_vgpr535_vgpr536_vgpr537_vgpr538_vgpr539_vgpr540_vgpr541_vgpr542_vgpr543, $vgpr544_vgpr545_vgpr546_vgpr547_vgpr548_vgpr549_vgpr550_vgpr551_vgpr552_vgpr553_vgpr554_vgpr555_vgpr556_vgpr557_vgpr558_vgpr559, $vgpr560_vgpr561_vgpr562_vgpr563_vgpr564_vgpr565_vgpr566_vgpr567_vgpr568_vgpr569_vgpr570_vgpr571_vgpr572_vgpr573_vgpr574_vgpr575, $vgpr576_vgpr577_vgpr578_vgpr579_vgpr580_vgpr581_vgpr582_vgpr583_vgpr584_vgpr585_vgpr586_vgpr587_vgpr588_vgpr589_vgpr590_vgpr591, $vgpr592_vgpr593_vgpr594_vgpr595_vgpr596_vgpr597_vgpr598_vgpr599_vgpr600_vgpr601_vgpr602_vgpr603_vgpr604_vgpr605_vgpr606_vgpr607, $vgpr608_vgpr609_vgpr610_vgpr611_vgpr612_vgpr613_vgpr614_vgpr615_vgpr616_vgpr617_vgpr618_vgpr619_vgpr620_vgpr621_vgpr622_vgpr623, $vgpr624_vgpr625_vgpr626_vgpr627_vgpr628_vgpr629_vgpr630_vgpr631_vgpr632_vgpr633_vgpr634_vgpr635_vgpr636_vgpr637_vgpr638_vgpr639, $vgpr768_vgpr769_vgpr770_vgpr771_vgpr772_vgpr773_vgpr774_vgpr775_vgpr776_vgpr777_vgpr778_vgpr779_vgpr780_vgpr781_vgpr782_vgpr783, $vgpr784_vgpr785_vgpr786_vgpr787_vgpr788_vgpr789_vgpr790_vgpr791_vgpr792_vgpr793_vgpr794_vgpr795_vgpr796_vgpr797_vgpr798_vgpr799, $vgpr800_vgpr801_vgpr802_vgpr803_vgpr804_vgpr805_vgpr806_vgpr807_vgpr808_vgpr809_vgpr810_vgpr811_vgpr812_vgpr813_vgpr814_vgpr815, $vgpr816_vgpr817_vgpr818_vgpr819_vgpr820_vgpr821_vgpr822_vgpr823_vgpr824_vgpr825_vgpr826_vgpr827_vgpr828_vgpr829_vgpr830_vgpr831, $vgpr832_vgpr833_vgpr834_vgpr835_vgpr836_vgpr837_vgpr838_vgpr839_vgpr840_vgpr841_vgpr842_vgpr843_vgpr844_vgpr845_vgpr846_vgpr847, $vgpr848_vgpr849_vgpr850_vgpr851_vgpr852_vgpr853_vgpr854_vgpr855_vgpr856_vgpr857_vgpr858_vgpr859_vgpr860_vgpr861_vgpr862_vgpr863, $vgpr864_vgpr865_vgpr866_vgpr867_vgpr868_vgpr869_vgpr870_vgpr871_vgpr872_vgpr873_vgpr874_vgpr875_vgpr876_vgpr877_vgpr878_vgpr879, $vgpr880_vgpr881_vgpr882_vgpr883_vgpr884_vgpr885_vgpr886_vgpr887_vgpr888_vgpr889_vgpr890_vgpr891_vgpr892_vgpr893_vgpr894_vgpr895
+
+ %0:vgpr_32_lo128 = IMPLICIT_DEF
+ %1:vgpr_32_lo128 = V_RCP_F16_fake16_e32 killed %0, implicit $mode, implicit $exec
+
+ S_ENDPGM 0, implicit %1, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263_vgpr264_vgpr265_vgpr266_vgpr267_vgpr268_vgpr269_vgpr270_vgpr271, implicit $vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277_vgpr278_vgpr279_vgpr280_vgpr281_vgpr282_vgpr283_vgpr284_vgpr285_vgpr286_vgpr287, implicit $vgpr288_vgpr289_vgpr290_vgpr291_vgpr292_vgpr293_vgpr294_vgpr295_vgpr296_vgpr297_vgpr298_vgpr299_vgpr300_vgpr301_vgpr302_vgpr303, implicit $vgpr304_vgpr305_vgpr306_vgpr307_vgpr308_vgpr309_vgpr310_vgpr311_vgpr312_vgpr313_vgpr314_vgpr315_vgpr316_vgpr317_vgpr318_vgpr319, implicit $vgpr320_vgpr321_vgpr322_vgpr323_vgpr324_vgpr325_vgpr326_vgpr327_vgpr328_vgpr329_vgpr330_vgpr331_vgpr332_vgpr333_vgpr334_vgpr335, implicit $vgpr336_vgpr337_vgpr338_vgpr339_vgpr340_vgpr341_vgpr342_vgpr343_vgpr344_vgpr345_vgpr346_vgpr347_vgpr348_vgpr349_vgpr350_vgpr351, implicit $vgpr352_vgpr353_vgpr354_vgpr355_vgpr356_vgpr357_vgpr358_vgpr359_vgpr360_vgpr361_vgpr362_vgpr363_vgpr364_vgpr365_vgpr366_vgpr367, implicit $vgpr368_vgpr369_vgpr370_vgpr371_vgpr372_vgpr373_vgpr374_vgpr375_vgpr376_vgpr377_vgpr378_vgpr379_vgpr380_vgpr381_vgpr382_vgpr383, implicit $vgpr512_vgpr513_vgpr514_vgpr515_vgpr516_vgpr517_vgpr518_vgpr519_vgpr520_vgpr521_vgpr522_vgpr523_vgpr524_vgpr525_vgpr526_vgpr527, implicit $vgpr528_vgpr529_vgpr530_vgpr531_vgpr532_vgpr533_vgpr534_vgpr535_vgpr536_vgpr537_vgpr538_vgpr539_vgpr540_vgpr541_vgpr542_vgpr543, implicit $vgpr544_vgpr545_vgpr546_vgpr547_vgpr548_vgpr549_vgpr550_vgpr551_vgpr552_vgpr553_vgpr554_vgpr555_vgpr556_vgpr557_vgpr558_vgpr559, implicit $vgpr560_vgpr561_vgpr562_vgpr563_vgpr564_vgpr565_vgpr566_vgpr567_vgpr568_vgpr569_vgpr570_vgpr571_vgpr572_vgpr573_vgpr574_vgpr575, implicit $vgpr576_vgpr577_vgpr578_vgpr579_vgpr580_vgpr581_vgpr582_vgpr583_vgpr584_vgpr585_vgpr586_vgpr587_vgpr588_vgpr589_vgpr590_vgpr591, implicit $vgpr592_vgpr593_vgpr594_vgpr595_vgpr596_vgpr597_vgpr598_vgpr599_vgpr600_vgpr601_vgpr602_vgpr603_vgpr604_vgpr605_vgpr606_vgpr607, implicit $vgpr608_vgpr609_vgpr610_vgpr611_vgpr612_vgpr613_vgpr614_vgpr615_vgpr616_vgpr617_vgpr618_vgpr619_vgpr620_vgpr621_vgpr622_vgpr623, implicit $vgpr624_vgpr625_vgpr626_vgpr627_vgpr628_vgpr629_vgpr630_vgpr631_vgpr632_vgpr633_vgpr634_vgpr635_vgpr636_vgpr637_vgpr638_vgpr639, implicit $vgpr768_vgpr769_vgpr770_vgpr771_vgpr772_vgpr773_vgpr774_vgpr775_vgpr776_vgpr777_vgpr778_vgpr779_vgpr780_vgpr781_vgpr782_vgpr783, implicit $vgpr784_vgpr785_vgpr786_vgpr787_vgpr788_vgpr789_vgpr790_vgpr791_vgpr792_vgpr793_vgpr794_vgpr795_vgpr796_vgpr797_vgpr798_vgpr799, implicit $vgpr800_vgpr801_vgpr802_vgpr803_vgpr804_vgpr805_vgpr806_vgpr807_vgpr808_vgpr809_vgpr810_vgpr811_vgpr812_vgpr813_vgpr814_vgpr815, implicit $vgpr816_vgpr817_vgpr818_vgpr819_vgpr820_vgpr821_vgpr822_vgpr823_vgpr824_vgpr825_vgpr826_vgpr827_vgpr828_vgpr829_vgpr830_vgpr831, implicit $vgpr832_vgpr833_vgpr834_vgpr835_vgpr836_vgpr837_vgpr838_vgpr839_vgpr840_vgpr841_vgpr842_vgpr843_vgpr844_vgpr845_vgpr846_vgpr847, implicit $vgpr848_vgpr849_vgpr850_vgpr851_vgpr852_vgpr853_vgpr854_vgpr855_vgpr856_vgpr857_vgpr858_vgpr859_vgpr860_vgpr861_vgpr862_vgpr863, implicit $vgpr864_vgpr865_vgpr866_vgpr867_vgpr868_vgpr869_vgpr870_vgpr871_vgpr872_vgpr873_vgpr874_vgpr875_vgpr876_vgpr877_vgpr878_vgpr879, implicit $vgpr880_vgpr881_vgpr882_vgpr883_vgpr884_vgpr885_vgpr886_vgpr887_vgpr888_vgpr889_vgpr890_vgpr891_vgpr892_vgpr893_vgpr894_vgpr895
+...
diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
index 8ac85fa9c41a2..bdb6ad8c237e6 100644
--- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
+++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
@@ -73,7 +73,7 @@ body: |
# (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
# Check that renaming (2) does not inadvertently rename (1).
# CHECK-LABEL: name: test2
-# CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %0.sub0, 1245194 /* regdef:VGPR_32 */, def dead %1.sub1, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %1.sub1(tied-def 5)
+# CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def undef %0.sub0, 1376266 /* regdef:VGPR_32 */, def dead %1.sub1, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %1.sub1(tied-def 5)
name: test2
body: |
bb.0:
@@ -81,7 +81,7 @@ body: |
bb.1:
undef %0.sub1:vreg_64 = V_ALIGNBIT_B32_e64 %0.sub0:vreg_64, %0.sub0:vreg_64, 16, implicit $exec
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %0.sub0:vreg_64, 1245194 /* regdef:VGPR_32 */, def %0.sub1:vreg_64, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0:vreg_64(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %0.sub1:vreg_64(tied-def 5)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def undef %0.sub0:vreg_64, 1376266 /* regdef:VGPR_32 */, def %0.sub1:vreg_64, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0:vreg_64(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %0.sub1:vreg_64(tied-def 5)
S_BRANCH %bb.1
...
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
index cdd68630bf4ff..b0ba54ca8383e 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
@@ -43,7 +43,7 @@ body: |
; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:areg_128_align2 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec :: (load (s128), addrspace 1)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vreg_128_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]]
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_vgprcd_e64_:%[0-9]+]]:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 [[COPY1]], [[COPY2]], [[COPY3]].sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3080201 /* reguse:VReg_64_Align2 */, [[V_MFMA_F64_4X4X4F64_vgprcd_e64_]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3604489 /* reguse:VReg_64_Align2 */, [[V_MFMA_F64_4X4X4F64_vgprcd_e64_]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
%1:av_64_align2 = COPY $vgpr0_vgpr1
@@ -51,7 +51,7 @@ body: |
%3:areg_128_align2 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec :: (load (s128), addrspace 1)
%4:vreg_128_align2 = COPY %3
%5:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %4.sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3080201 /* reguse:VReg_64_Align2 */, %5
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3604489 /* reguse:VReg_64_Align2 */, %5
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
index d7b713aa53b86..c3dc218045b78 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
@@ -19,7 +19,7 @@ body: |
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_e64_:%[0-9]+]]:areg_64_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[GLOBAL_LOAD_DWORDX2_]], 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2_sub3:areg_128_align2 = IMPLICIT_DEF
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], [[COPY3]].sub2_sub3, 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
@@ -30,7 +30,7 @@ body: |
%4:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %3, 0, 0, 0, implicit $mode, implicit $exec
undef %5.sub0_sub1:areg_128_align2 = COPY %4
%5.sub2_sub3 = IMPLICIT_DEF
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %5
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %5
GLOBAL_STORE_DWORDX4 %0, %5, 0, 0, implicit $exec :: (store (s128), addrspace 1)
GLOBAL_STORE_DWORDX2 %0, %5.sub2_sub3, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
@@ -172,7 +172,7 @@ body: |
; CHECK-NEXT: undef [[V_MFMA_F64_4X4X4F64_e64_:%[0-9]+]].sub2_sub3:areg_128_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[GLOBAL_LOAD_DWORDX2_]], 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub2_sub3
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2_sub3:areg_128_align2 = IMPLICIT_DEF
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], [[COPY3]].sub2_sub3, 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
@@ -183,7 +183,7 @@ body: |
undef %4.sub2_sub3:vreg_128_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %3, 0, 0, 0, implicit $mode, implicit $exec
undef %5.sub0_sub1:areg_128_align2 = COPY %4.sub2_sub3
%5.sub2_sub3 = IMPLICIT_DEF
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %5
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %5
GLOBAL_STORE_DWORDX4 %0, %5, 0, 0, implicit $exec :: (store (s128), addrspace 1)
GLOBAL_STORE_DWORDX2 %0, %5.sub2_sub3, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
@@ -208,7 +208,7 @@ body: |
; CHECK-NEXT: undef [[V_MFMA_F64_4X4X4F64_vgprcd_e64_:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 [[COPY1]], [[COPY2]], [[GLOBAL_LOAD_DWORDX2_]], 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub1:areg_128_align2 = COPY [[V_MFMA_F64_4X4X4F64_vgprcd_e64_]].sub2
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2_sub3:areg_128_align2 = IMPLICIT_DEF
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], [[COPY3]].sub2_sub3, 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
@@ -219,7 +219,7 @@ body: |
undef %4.sub2_sub3:vreg_128_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %3, 0, 0, 0, implicit $mode, implicit $exec
undef %5.sub1:areg_128_align2 = COPY %4.sub2
%5.sub2_sub3 = IMPLICIT_DEF
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %5
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %5
GLOBAL_STORE_DWORDX4 %0, %5, 0, 0, implicit $exec :: (store (s128), addrspace 1)
GLOBAL_STORE_DWORDX2 %0, %5.sub2_sub3, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
index 3f61c3dbfaf37..852561b025c6d 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
@@ -17,7 +17,7 @@ body: |
; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:areg_128_align2 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec :: (load (s128), addrspace 1)
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_e64_:%[0-9]+]]:areg_64_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -26,7 +26,7 @@ body: |
%3:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec :: (load (s128), addrspace 1)
%4:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %3.sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
undef %5.sub0_sub1:areg_128_align2 = COPY %4
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %5
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %5
GLOBAL_STORE_DWORDX4 %0, %5, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
...
@@ -47,7 +47,7 @@ body: |
; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:areg_128_align2 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec :: (load (s128), addrspace 1)
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_e64_:%[0-9]+]]:areg_64_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[GLOBAL_LOAD_DWORDX4_]].sub2_sub3, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -56,7 +56,7 @@ body: |
%3:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec :: (load (s128), addrspace 1)
%4:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %3.sub2_sub3, 0, 0, 0, implicit $mode, implicit $exec
undef %5.sub0_sub1:areg_128_align2 = COPY %4
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %5
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %5
GLOBAL_STORE_DWORDX4 %0, %5, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
...
@@ -79,7 +79,7 @@ body: |
; CHECK-NEXT: dead %other_use:vreg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub0_sub1
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_e64_1:%[0-9]+]]:areg_64_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[V_MFMA_F64_4X4X4F64_e64_]].sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[COPY3:%[0-9]+]]:areg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -90,7 +90,7 @@ body: |
%other_use:vreg_64_align2 = COPY %4.sub0_sub1
%5:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %4.sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
%6:areg_64_align2 = COPY %5
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %6:areg_64_align2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %6:areg_64_align2
GLOBAL_STORE_DWORDX2 %0, %6, 0, 0, implicit $exec :: (store (s64), addrspace 1)
SI_RETURN
...
@@ -114,7 +114,7 @@ body: |
; CHECK-NEXT: undef [[V_MFMA_F64_4X4X4F64_e64_1:%[0-9]+]].sub0_sub1:areg_128_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[V_MFMA_F64_4X4X4F64_e64_]], 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_e64_2:%[0-9]+]]:areg_64_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[V_MFMA_F64_4X4X4F64_e64_1]].sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[COPY3:%[0-9]+]]:areg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4259849 /* reguse:AReg_64_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -126,7 +126,7 @@ body: |
undef %5.sub0_sub1:vreg_128_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %4, 0, 0, 0, implicit $mode, implicit $exec
%6:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %5.sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
%7:areg_64_align2 = COPY %6
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64_Align2 */, %7
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4259849 /* reguse:AReg_64_Align2 */, %7
GLOBAL_STORE_DWORDX2 %0, %7, 0, 0, implicit $exec :: (store (s64), addrspace 1)
SI_RETURN
@@ -151,7 +151,7 @@ body: |
; CHECK-NEXT: dead %other_use:vreg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_1]].sub0_sub1
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_e64_2:%[0-9]+]]:areg_64_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[V_MFMA_F64_4X4X4F64_e64_1]].sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -163,7 +163,7 @@ body: |
%other_use:vreg_64_align2 = COPY %5.sub0_sub1
%6:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %5.sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
undef %8.sub0_sub1:areg_128_align2 = COPY %6
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %8:areg_128_align2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %8:areg_128_align2
GLOBAL_STORE_DWORDX4 %0, %8, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
@@ -189,7 +189,7 @@ body: |
; CHECK-NEXT: dead %other_use1:vreg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_1]].sub0_sub1
; CHECK-NEXT: [[V_MFMA_F64_4X4X4F64_e64_2:%[0-9]+]]:areg_64_align2 = V_MFMA_F64_4X4X4F64_e64 [[COPY1]], [[COPY2]], [[V_MFMA_F64_4X4X4F64_e64_1]].sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[V_MFMA_F64_4X4X4F64_e64_2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1638409 /* reguse:AGPR_32 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:AGPR_32 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORD [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s32), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -202,7 +202,7 @@ body: |
%other_use1:vreg_64_align2 = COPY %5.sub0_sub1
%6:vreg_64_align2 = V_MFMA_F64_4X4X4F64_vgprcd_e64 %1, %2, %5.sub0_sub1, 0, 0, 0, implicit $mode, implicit $exec
%8:agpr_32 = COPY %6
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1638409 /* reguse:AGPR_32 */, %8:agpr_32
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:AGPR_32 */, %8:agpr_32
GLOBAL_STORE_DWORD %0, %8, 0, 0, implicit $exec :: (store (s32), addrspace 1)
SI_RETURN
@@ -231,7 +231,7 @@ body: |
; CHECK-NEXT: dead %other_use1:vreg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub2_sub3
; CHECK-NEXT: dead %other_use2:vreg_64 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub1_sub2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:areg_128_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 [[COPY]], [[COPY3]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -245,7 +245,7 @@ body: |
%other_use1:vreg_64_align2 = COPY %4.sub2_sub3
%other_use2:vreg_64 = COPY %4.sub1_sub2
%6:areg_128_align2 = COPY %4
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8650761 /* reguse:AReg_128_Align2 */, %6:areg_128_align2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10092553 /* reguse:AReg_128_Align2 */, %6:areg_128_align2
GLOBAL_STORE_DWORDX4 %0, %6, 0, 0, implicit $exec :: (store (s128), addrspace 1)
SI_RETURN
...
@@ -273,7 +273,7 @@ body: |
; CHECK-NEXT: %other_use1:vreg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub2_sub3
; CHECK-NEXT: dead %other_use2:vreg_64 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub1_sub2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:areg_64 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], %other_use1, 0, 0, implicit $exec :: (store (s64), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -287,7 +287,7 @@ body: |
%other_use1:vreg_64_align2 = COPY %4.sub2_sub3
%other_use2:vreg_64 = COPY %4.sub1_sub2
%6:areg_64 = COPY %4.sub1_sub2
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3407881 /* reguse:AReg_64 */, %6:areg_64
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64 */, %6:areg_64
GLOBAL_STORE_DWORDX2 %0, %other_use1, 0, 0, implicit $exec :: (store (s64), addrspace 1)
SI_RETURN
...
@@ -313,7 +313,7 @@ body: |
; CHECK-NEXT: %other_use1:vreg_64_align2 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub2_sub3
; CHECK-NEXT: dead %other_use2:vreg_64 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub1_sub2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:areg_64 = COPY [[V_MFMA_F64_4X4X4F64_e64_]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3407881 /* reguse:AReg_64 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64 */, [[COPY3]]
; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], %other_use1, 0, 0, implicit $exec :: (store (s64), addrspace 1)
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr4_vgpr5
@@ -327,7 +327,7 @@ body: |
%other_use1:vreg_64_align2 = COPY %4.sub2_sub3
%other_use2:vreg_64 = COPY %4.sub1_sub2
%6:areg_64 = COPY %4.sub1_sub2
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3407881 /* reguse:AReg_64 */, %6:areg_64
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:AReg_64 */, %6:areg_64
GLOBAL_STORE_DWORDX2 %0, %other_use1, 0, 0, implicit $exec :: (store (s64), addrspace 1)
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
index b754a6b897159..f0591a0728c93 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
@@ -37,7 +37,7 @@ body: |
; CHECK-NEXT: dead [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub1:vreg_512 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def dead [[COPY1]], 1245194 /* regdef:VGPR_32 */, def dead [[COPY]].sub1, 1245193 /* reguse:VGPR_32 */, [[COPY1]], 1245193 /* reguse:VGPR_32 */, [[COPY]].sub1
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def dead [[COPY1]], 1376266 /* regdef:VGPR_32 */, def dead [[COPY]].sub1, 1376265 /* reguse:VGPR_32 */, [[COPY1]], 1376265 /* reguse:VGPR_32 */, [[COPY]].sub1
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub0:vreg_512 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub3:vreg_512 = COPY [[COPY]].sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_1]]
@@ -63,7 +63,7 @@ body: |
undef %11.sub0:vreg_512 = COPY %4.sub0
%12:vgpr_32 = COPY %4.sub0
%11.sub1:vreg_512 = COPY %4.sub1
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def dead %12:vgpr_32, 1245194 /* regdef:VGPR_32 */, def dead %4.sub1:vreg_512, 1245193 /* reguse:VGPR_32 */, %12:vgpr_32, 1245193 /* reguse:VGPR_32 */, %4.sub1:vreg_512
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def dead %12:vgpr_32, 1376266 /* regdef:VGPR_32 */, def dead %4.sub1:vreg_512, 1376265 /* reguse:VGPR_32 */, %12:vgpr_32, 1376265 /* reguse:VGPR_32 */, %4.sub1:vreg_512
%11.sub2:vreg_512 = COPY undef %1
%11.sub3:vreg_512 = COPY %4.sub3
%11.sub5:vreg_512 = COPY undef %1
diff --git a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
index 5edb9669d98eb..9b0a471bf37c3 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
@@ -40,18 +40,18 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def dead %11
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def dead %11
; CHECK-NEXT: GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, implicit $exec :: (store (s32), addrspace 1)
; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load (s64), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %15, 1245194 /* regdef:VGPR_32 */, def %16
+ ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %15, 1376266 /* regdef:VGPR_32 */, def %16
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
; CHECK-NEXT: [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_2]], 0, 0, implicit $exec
; CHECK-NEXT: [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
- ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %21, 1245194 /* regdef:VGPR_32 */, def %22
+ ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %21, 1376266 /* regdef:VGPR_32 */, def %22
; CHECK-NEXT: [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_2]], 0, 0, implicit $exec
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def dead [[V_MOV_B32_e32_3]], 1245194 /* regdef:VGPR_32 */, def dead [[V_MOV_B32_e32_4]], 1245193 /* reguse:VGPR_32 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_3]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_4]](tied-def 5), 1245193 /* reguse:VGPR_32 */, %15, 1245193 /* reguse:VGPR_32 */, %16, 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_1]], 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]], 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_3]], 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_2]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def dead [[V_MOV_B32_e32_3]], 1376266 /* regdef:VGPR_32 */, def dead [[V_MOV_B32_e32_4]], 1376265 /* reguse:VGPR_32 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_3]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_4]](tied-def 5), 1376265 /* reguse:VGPR_32 */, %15, 1376265 /* reguse:VGPR_32 */, %16, 1376265 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_1]], 1376265 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]], 1376265 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_3]], 1376265 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_2]]
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_1]]
; CHECK-NEXT: DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store (s32), addrspace 3)
; CHECK-NEXT: DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store (s32), addrspace 3)
@@ -94,21 +94,21 @@ body: |
%10:vgpr_32 = IMPLICIT_DEF
bb.1:
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %11:vgpr_32
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %11:vgpr_32
GLOBAL_STORE_DWORD undef %12:vreg_64, %1, 0, 0, implicit $exec :: (store (s32), addrspace 1)
%13:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load (s64), addrspace 3)
- INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %15:vgpr_32, 1245194 /* regdef:VGPR_32 */, def %16:vgpr_32
+ INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %15:vgpr_32, 1376266 /* regdef:VGPR_32 */, def %16:vgpr_32
%17:vgpr_32 = DS_READ_B32_gfx9 %6, 0, 0, implicit $exec
%18:vgpr_32 = DS_READ_B32_gfx9 %7, 0, 0, implicit $exec
%19:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
- INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %21:vgpr_32, 1245194 /* regdef:VGPR_32 */, def %22:vgpr_32
+ INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %21:vgpr_32, 1376266 /* regdef:VGPR_32 */, def %22:vgpr_32
%23:vgpr_32 = DS_READ_B32_gfx9 %7, 0, 0, implicit $exec
%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%5.sub1:vreg_64 = COPY %6
%25:vgpr_32 = V_ADD_U32_e32 1, %10, implicit $exec
%26:sreg_64_xexec = V_CMP_GT_U32_e64 64, %25, implicit $exec
%27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def dead %24:vgpr_32, 1245194 /* regdef:VGPR_32 */, def dead %27:vgpr_32, 1245193 /* reguse:VGPR_32 */, %13.sub0:vreg_64, 2147483657 /* reguse tiedto:$0 */, %24:vgpr_32(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %27:vgpr_32(tied-def 5), 1245193 /* reguse:VGPR_32 */, %15, 1245193 /* reguse:VGPR_32 */, %16, 1245193 /* reguse:VGPR_32 */, %18, 1245193 /* reguse:VGPR_32 */, %17, 1245193 /* reguse:VGPR_32 */, %23, 1245193 /* reguse:VGPR_32 */, %19
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def dead %24:vgpr_32, 1376266 /* regdef:VGPR_32 */, def dead %27:vgpr_32, 1376265 /* reguse:VGPR_32 */, %13.sub0:vreg_64, 2147483657 /* reguse tiedto:$0 */, %24:vgpr_32(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %27:vgpr_32(tied-def 5), 1376265 /* reguse:VGPR_32 */, %15, 1376265 /* reguse:VGPR_32 */, %16, 1376265 /* reguse:VGPR_32 */, %18, 1376265 /* reguse:VGPR_32 */, %17, 1376265 /* reguse:VGPR_32 */, %23, 1376265 /* reguse:VGPR_32 */, %19
DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store (s32), addrspace 3)
DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store (s32), addrspace 3)
DS_WRITE_B64_gfx9 undef %30:vgpr_32, %5, 0, 0, implicit $exec :: (store (s64), addrspace 3)
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
new file mode 100644
index 0000000000000..8a2447d31297b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
@@ -0,0 +1,89 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=si-shrink-instructions -o - %s | FileCheck --check-prefix=GCN %s
+
+# GCN-LABEL: name: rcp_f16_v127
+# GCN: $vgpr127 = V_RCP_F16_fake16_e32 killed $vgpr127
+---
+name: rcp_f16_v127
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr127 = IMPLICIT_DEF
+ $vgpr127 = V_RCP_F16_fake16_e64 0, killed $vgpr127, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: rcp_f16_v128
+# GCN: $vgpr128 = V_RCP_F16_fake16_e64 0, killed $vgpr128
+---
+name: rcp_f16_v128
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr128 = IMPLICIT_DEF
+ $vgpr128 = V_RCP_F16_fake16_e64 0, killed $vgpr128, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: rcp_f16_v256
+# GCN: $vgpr256 = V_RCP_F16_fake16_e32 killed $vgpr256
+---
+name: rcp_f16_v256
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr256 = IMPLICIT_DEF
+ $vgpr256 = V_RCP_F16_fake16_e64 0, killed $vgpr256, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: rcp_f16_v384
+# GCN: $vgpr384 = V_RCP_F16_fake16_e64 0, killed $vgpr384
+---
+name: rcp_f16_v384
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr384 = IMPLICIT_DEF
+ $vgpr384 = V_RCP_F16_fake16_e64 0, killed $vgpr384, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: rcp_f16_v512
+# GCN: $vgpr512 = V_RCP_F16_fake16_e32 killed $vgpr512
+---
+name: rcp_f16_v512
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr512 = IMPLICIT_DEF
+ $vgpr512 = V_RCP_F16_fake16_e64 0, killed $vgpr512, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: rcp_f16_v767
+# GCN: $vgpr767 = V_RCP_F16_fake16_e64 0, killed $vgpr767
+---
+name: rcp_f16_v767
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr767 = IMPLICIT_DEF
+ $vgpr767 = V_RCP_F16_fake16_e64 0, killed $vgpr767, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: rcp_f16_v768
+# GCN: $vgpr768 = V_RCP_F16_fake16_e32 killed $vgpr768
+---
+name: rcp_f16_v768
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr768 = IMPLICIT_DEF
+ $vgpr768 = V_RCP_F16_fake16_e64 0, killed $vgpr768, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: rcp_f16_v1023
+# GCN: $vgpr1023 = V_RCP_F16_fake16_e64 0, killed $vgpr1023
+---
+name: rcp_f16_v1023
+tracksRegLiveness: true
+body: |
+ bb.0:
+ $vgpr1023 = IMPLICIT_DEF
+ $vgpr1023 = V_RCP_F16_fake16_e64 0, killed $vgpr1023, 0, 0, implicit $mode, implicit $exec
+...
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
index 8ecc0ad65a944..7c77a95d8f33c 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
@@ -12,10 +12,10 @@ define amdgpu_kernel void @test_spill_av_class(<4 x i32> %arg) #0 {
; GCN-NEXT: [[AV_MOV_:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 1, implicit $exec
; GCN-NEXT: [[AV_MOV_1:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 2, implicit $exec
; GCN-NEXT: [[V_MFMA_I32_4X4X4I8_e64_:%[0-9]+]]:areg_128 = V_MFMA_I32_4X4X4I8_e64 [[AV_MOV_]], [[AV_MOV_1]], [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %14.sub0
+ ; GCN-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def undef %14.sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_I32_4X4X4I8_e64_]]
; GCN-NEXT: GLOBAL_STORE_DWORDX4 undef %24:vreg_64, [[COPY1]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
- ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2818057 /* reguse:VReg_64 */, %14
+ ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2883593 /* reguse:VReg_64 */, %14
; GCN-NEXT: S_ENDPGM 0
%v0 = call i32 asm sideeffect "; def $0", "=v"()
%tmp = insertelement <2 x i32> poison, i32 %v0, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
index 2fd1e36c4181e..2405f9f7dbc8f 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
+++ b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
@@ -28,9 +28,9 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def [[V_MOV_B32_e32_]], 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_]](tied-def 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]]
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub0, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub1
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def [[V_MOV_B32_e32_]], 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub0, 1376266 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
; CHECK-NEXT: S_BRANCH %bb.1
@@ -41,9 +41,9 @@ body: |
bb.1:
%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %2
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %0.sub0, 1245194 /* regdef:VGPR_32 */, def %0.sub1
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %2
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def undef %0.sub0, 1376266 /* regdef:VGPR_32 */, def %0.sub1
S_NOP 0, implicit %0.sub1
$sgpr10 = S_MOV_B32 -1
S_BRANCH %bb.1
@@ -69,9 +69,9 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def [[V_MOV_B32_e32_]], 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_]](tied-def 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]]
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub1, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def [[V_MOV_B32_e32_]], 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub1, 1376266 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub0
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
; CHECK-NEXT: S_BRANCH %bb.1
@@ -82,9 +82,9 @@ body: |
bb.1:
%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %2
- INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %0.sub1, 1245194 /* regdef:VGPR_32 */, def undef %0.sub0
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376265 /* reguse:VGPR_32 */, %2
+ INLINEASM &"", 1 /* sideeffect attdialect */, 1376266 /* regdef:VGPR_32 */, def %0.sub1, 1376266 /* regdef:VGPR_32 */, def undef %0.sub0
S_NOP 0, implicit %0.sub1
$sgpr10 = S_MOV_B32 -1
S_BRANCH %bb.1
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
index c4ffef54a866d..f43e0d647148b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
@@ -95,11 +95,11 @@
# GFX11-REAL16: v_ceil_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb8,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xb8,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_ceil_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb8,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_ceil_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb8,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb8,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_ceil_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_ceil_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -289,11 +289,11 @@
# GFX11-REAL16: v_cos_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc2,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xc2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cos_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_cos_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc2,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_cos_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_cos_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -429,11 +429,11 @@
# GFX11-REAL16: v_cvt_f16_f32_dpp v127.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x14,0xfe,0x7e,0x01,0x5f,0x01,0x01]
0xfa,0x14,0x0a,0x7f,0x01,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, s1, v176 ; encoding: [0x01,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cvt_f16_f32_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7f,0x01,0x60,0x01,0x13]
# GFX11-REAL16: v_cvt_f16_f32_dpp v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7f,0x01,0x60,0x01,0x13]
0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_cvt_f16_f32_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_cvt_f16_f32_dpp v127.h, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -485,11 +485,11 @@
# GFX11-REAL16: v_cvt_f16_i16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa2,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xa2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cvt_f16_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_cvt_f16_i16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa2,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX11-FAKE16: v_cvt_f16_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX11-REAL16: v_cvt_f16_i16_dpp v127.h, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -541,11 +541,11 @@
# GFX11-REAL16: v_cvt_f16_u16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa0,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xa0,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cvt_f16_u16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa0,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_cvt_f16_u16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa0,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa0,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX11-FAKE16: v_cvt_f16_u16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa0,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX11-REAL16: v_cvt_f16_u16_dpp v127.h, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa0,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -947,11 +947,11 @@
# GFX11-REAL16: v_cvt_i16_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa6,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xa6,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cvt_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa6,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_cvt_i16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa6,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa6,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_cvt_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_cvt_i16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1155,11 +1155,11 @@
# GFX11-REAL16: v_cvt_norm_i16_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc6,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xc6,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cvt_norm_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc6,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_cvt_norm_i16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc6,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc6,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_cvt_norm_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_cvt_norm_i16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1211,11 +1211,11 @@
# GFX11-REAL16: v_cvt_norm_u16_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc8,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xc8,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cvt_norm_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc8,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_cvt_norm_u16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc8,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc8,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_cvt_norm_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_cvt_norm_u16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1309,11 +1309,11 @@
# GFX11-REAL16: v_cvt_u16_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa4,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xa4,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_cvt_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa4,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_cvt_u16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa4,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa4,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_cvt_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_cvt_u16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1475,11 +1475,11 @@
# GFX11-REAL16: v_exp_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb0,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xb0,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_exp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb0,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_exp_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb0,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb0,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_exp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_exp_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1573,11 +1573,11 @@
# GFX11-REAL16: v_floor_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb6,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xb6,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_floor_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb6,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_floor_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb6,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb6,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_floor_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_floor_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1683,11 +1683,11 @@
# GFX11-REAL16: v_fract_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xbe,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xbe,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_fract_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbe,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_fract_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbe,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xbe,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_fract_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbe,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_fract_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbe,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1781,11 +1781,11 @@
# GFX11-REAL16: v_frexp_exp_i16_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb4,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xb4,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_frexp_exp_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb4,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_frexp_exp_i16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb4,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb4,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_frexp_exp_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_frexp_exp_i16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1891,11 +1891,11 @@
# GFX11-REAL16: v_frexp_mant_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb2,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xb2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_frexp_mant_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb2,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_frexp_mant_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_frexp_mant_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1989,11 +1989,11 @@
# GFX11-REAL16: v_log_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xae,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xae,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_log_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xae,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_log_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xae,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xae,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_log_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xae,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_log_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xae,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2309,11 +2309,11 @@
# GFX11-REAL16: v_not_b16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xd2,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xd2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_not_b16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xd2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_not_b16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xd2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xd2,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX11-FAKE16: v_not_b16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX11-REAL16: v_not_b16_dpp v127.h, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2407,11 +2407,11 @@
# GFX11-REAL16: v_rcp_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa8,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xa8,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_rcp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa8,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_rcp_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa8,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa8,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_rcp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_rcp_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2559,11 +2559,11 @@
# GFX11-REAL16: v_rndne_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xbc,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xbc,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_rndne_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbc,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_rndne_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbc,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xbc,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_rndne_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbc,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_rndne_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbc,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2657,11 +2657,11 @@
# GFX11-REAL16: v_rsq_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xac,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xac,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_rsq_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xac,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_rsq_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xac,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xac,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_rsq_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xac,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_rsq_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xac,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2767,11 +2767,11 @@
# GFX11-REAL16: v_sat_pk_u8_i16_dpp v127.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc4,0xfe,0x7e,0x01,0x5f,0x01,0x01]
0xfa,0xc4,0x0a,0x7f,0x01,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, s1, v176 ; encoding: [0x01,0x60,0x01,0x13]
+# GFX11-FAKE16: v_sat_pk_u8_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc4,0x0a,0x7f,0x01,0x60,0x01,0x13]
# GFX11-REAL16: v_sat_pk_u8_i16_dpp v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc4,0x0a,0x7f,0x01,0x60,0x01,0x13]
0xfa,0xc4,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX11-FAKE16: v_sat_pk_u8_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX11-REAL16: v_sat_pk_u8_i16_dpp v127.h, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2835,11 +2835,11 @@
# GFX11-REAL16: v_sin_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_sin_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_sin_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_sin_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_sin_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2933,11 +2933,11 @@
# GFX11-REAL16: v_sqrt_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xaa,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xaa,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_sqrt_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xaa,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_sqrt_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xaa,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xaa,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_sqrt_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xaa,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_sqrt_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xaa,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -3043,11 +3043,11 @@
# GFX11-REAL16: v_trunc_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xba,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
0xfa,0xba,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_trunc_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xba,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_trunc_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xba,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xba,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX11-FAKE16: v_trunc_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xba,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX11-REAL16: v_trunc_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xba,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
index 062532e1899f1..6c5f97508202f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
@@ -18,10 +18,11 @@
# GFX11-REAL16: v_ceil_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb8,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_ceil_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_ceil_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_ceil_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_ceil_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -55,10 +56,11 @@
# GFX11-REAL16: v_cos_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cos_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_cos_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cos_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cos_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x6c,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -82,10 +84,11 @@
# GFX11-REAL16: v_cvt_f16_f32_dpp v127.l, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x14,0xfe,0x7e,0x01,0x77,0x39,0x05]
0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v1, v187 ; encoding: [0x01,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cvt_f16_f32_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05]
# GFX11-REAL16: v_cvt_f16_f32_dpp v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05]
0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cvt_f16_f32_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cvt_f16_f32_dpp v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xa2,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -97,10 +100,11 @@
# GFX11-REAL16: v_cvt_f16_i16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cvt_f16_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_cvt_f16_i16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cvt_f16_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cvt_f16_i16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xa0,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -112,10 +116,11 @@
# GFX11-REAL16: v_cvt_f16_u16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa0,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cvt_f16_u16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_cvt_f16_u16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cvt_f16_u16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cvt_f16_u16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -185,10 +190,11 @@
# GFX11-REAL16: v_cvt_i16_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa6,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cvt_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_cvt_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cvt_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cvt_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x10,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -232,10 +238,11 @@
# GFX11-REAL16: v_cvt_norm_i16_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc6,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cvt_norm_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_cvt_norm_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cvt_norm_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cvt_norm_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xc8,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -247,10 +254,11 @@
# GFX11-REAL16: v_cvt_norm_u16_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc8,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cvt_norm_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_cvt_norm_u16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cvt_norm_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cvt_norm_u16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x1c,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -268,10 +276,11 @@
# GFX11-REAL16: v_cvt_u16_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa4,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_cvt_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_cvt_u16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_cvt_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_cvt_u16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x0e,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -309,10 +318,11 @@
# GFX11-REAL16: v_exp_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb0,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_exp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_exp_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_exp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_exp_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x4a,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -330,10 +340,11 @@
# GFX11-REAL16: v_floor_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb6,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_floor_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_floor_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_floor_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_floor_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x48,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -355,10 +366,11 @@
# GFX11-REAL16: v_fract_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbe,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_fract_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_fract_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_fract_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_fract_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x40,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -376,10 +388,11 @@
# GFX11-REAL16: v_frexp_exp_i16_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb4,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_frexp_exp_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_frexp_exp_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_frexp_exp_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_frexp_exp_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x7e,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -409,11 +422,12 @@
# GFX11-REAL16-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_frexp_mant_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16-REAL16: v_frexp_mant_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_frexp_mant_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_frexp_mant_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xea,0x80,0xfe,0x7f,0xff,0x00,0x00,0x00
@@ -428,10 +442,11 @@
# GFX11-REAL16: v_log_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xae,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_log_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_log_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_log_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_log_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x4e,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -483,10 +498,11 @@
# GFX11-REAL16: v_not_b16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_not_b16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_not_b16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_not_b16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_not_b16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x6e,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -504,10 +520,11 @@
# GFX11-REAL16: v_rcp_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa8,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_rcp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_rcp_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_rcp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_rcp_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x54,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -535,10 +552,11 @@
# GFX11-REAL16: v_rndne_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbc,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_rndne_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_rndne_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_rndne_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_rndne_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x46,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -556,10 +574,11 @@
# GFX11-REAL16: v_rsq_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xac,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_rsq_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_rsq_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_rsq_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_rsq_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x5c,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -581,10 +600,11 @@
# GFX11-REAL16: v_sat_pk_u8_i16_dpp v127.l, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc4,0xfe,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v1, v187 ; encoding: [0x01,0x77,0x39,0x05]
+# GFX11-FAKE16: v_sat_pk_u8_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05]
# GFX11-REAL16: v_sat_pk_u8_i16_dpp v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05]
0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_sat_pk_u8_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_sat_pk_u8_i16_dpp v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -600,10 +620,11 @@
# GFX11-REAL16: v_sin_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_sin_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_sin_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_sin_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_sin_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -621,10 +642,11 @@
# GFX11-REAL16: v_sqrt_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xaa,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_sqrt_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_sqrt_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_sqrt_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_sqrt_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x66,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -646,10 +668,11 @@
# GFX11-REAL16: v_trunc_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0xfe,0x7e,0x7f,0x77,0x39,0x05]
0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_trunc_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_trunc_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_trunc_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_trunc_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x42,0x0a,0x7e,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
index a0a762e2fa343..55f49fa350ffe 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
@@ -109,11 +109,11 @@
# GFX11-REAL16: v_add_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x5f,0x01,0x01]
0xfa,0x04,0x0b,0x65,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_add_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x65,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_add_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x65,0x81,0x60,0x01,0x13]
0xfa,0xfe,0xff,0x65,0xff,0x6f,0xfd,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX11-FAKE16: v_add_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x65,0xff,0x6f,0xfd,0x30]
# GFX11-REAL16: v_add_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x65,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff
@@ -485,11 +485,11 @@
# GFX11-REAL16: v_fmac_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x5f,0x01,0x01]
0xfa,0x04,0x0b,0x6d,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_fmac_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x6d,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_fmac_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x6d,0x81,0x60,0x01,0x13]
0xfa,0xfe,0xff,0x6d,0xff,0x6f,0xfd,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX11-FAKE16: v_fmac_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6d,0xff,0x6f,0xfd,0x30]
# GFX11-REAL16: v_fmac_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6d,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff
@@ -1493,11 +1493,11 @@
# GFX11-REAL16: v_sub_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x5f,0x01,0x01]
0xfa,0x04,0x0b,0x67,0x81,0x60,0x01,0x13
-# GFX11-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX11-FAKE16: v_sub_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x67,0x81,0x60,0x01,0x13]
# GFX11-REAL16: v_sub_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x67,0x81,0x60,0x01,0x13]
0xfa,0xfe,0xff,0x67,0xff,0x6f,0xfd,0x30
-# GFX11-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX11-FAKE16: v_sub_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x67,0xff,0x6f,0xfd,0x30]
# GFX11-REAL16: v_sub_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x67,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
index 2223a0c9c2c15..3603eead47ada 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
@@ -21,10 +21,11 @@
# GFX11-REAL16: v_add_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x64,0x7f,0x77,0x39,0x05]
0xe9,0x04,0x0b,0x65,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_add_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x65,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_add_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x65,0x81,0x77,0x39,0x05]
0xea,0xfe,0xff,0x65,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_add_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x65,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_add_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x65,0xff,0x00,0x00,0x00]
0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05
@@ -80,10 +81,11 @@
# GFX11-REAL16: v_fmac_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x6c,0x7f,0x77,0x39,0x05]
0xe9,0x04,0x0b,0x6d,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_fmac_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x6d,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_fmac_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x6d,0x81,0x77,0x39,0x05]
0xea,0xfe,0xff,0x6d,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_fmac_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x6d,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_fmac_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x6d,0xff,0x00,0x00,0x00]
0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05
@@ -231,10 +233,11 @@
# GFX11-REAL16: v_sub_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x66,0x7f,0x77,0x39,0x05]
0xe9,0x04,0x0b,0x67,0x81,0x77,0x39,0x05
-# GFX11-FAKE16: v_dot2acc_f32_f16 v156, v129, v187 ; encoding: [0x81,0x77,0x39,0x05]
+# GFX11-FAKE16: v_sub_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x67,0x81,0x77,0x39,0x05]
# GFX11-REAL16: v_sub_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x67,0x81,0x77,0x39,0x05]
0xea,0xfe,0xff,0x67,0xff,0x00,0x00,0x00
+# GFX11-FAKE16: v_sub_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x67,0xff,0x00,0x00,0x00]
# GFX11-REAL16: v_sub_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x67,0xff,0x00,0x00,0x00]
0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
index 7ece29be4aefb..64cd854301fbf 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
@@ -24,7 +24,7 @@
# GFX1250-REAL16: v_tanh_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x3e,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0x3e,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x3e,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_tanh_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x3e,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -40,7 +40,7 @@
# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_tanh_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0x96,0xfe,0x7f,0xff,0x00,0x00,0x00
@@ -65,7 +65,7 @@
# GFX1250-REAL16: v_rcp_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xf2,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xf2,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_rcp_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_rcp_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf2,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xf4,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -81,7 +81,7 @@
# GFX1250-REAL16: v_sqrt_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xf4,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xf4,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_sqrt_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf4,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_sqrt_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf4,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xf6,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -97,7 +97,7 @@
# GFX1250-REAL16: v_rsq_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xf6,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xf6,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_rsq_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf6,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_rsq_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf6,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xf8,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -113,7 +113,7 @@
# GFX1250-REAL16: v_log_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xf8,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xf8,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_log_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf8,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_log_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf8,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xfa,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -129,7 +129,7 @@
# GFX1250-REAL16: v_exp_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xfa,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xfa,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_exp_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfa,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_exp_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfa,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xfc,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -145,7 +145,7 @@
# GFX1250-REAL16: v_sin_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xfc,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xfc,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_sin_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfc,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_sin_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfc,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xfe,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -161,7 +161,7 @@
# GFX1250-REAL16: v_cos_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xfe,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0xfe,0x0a,0x7f,0x81,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_cos_bf16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX1250-REAL16: v_cos_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x0a,0x7f,0x81,0x77,0x39,0x05]
0xe9,0xe4,0xfe,0x7e,0x7f,0x00,0x00,0x00
@@ -185,7 +185,7 @@
# GFX1250-REAL16: v_cvt_f16_bf8_dpp v1.l, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf0,0x02,0x7e,0x02,0x77,0x39,0x05]
0xe9,0xf0,0x02,0x7f,0x02,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_cvt_f16_bf8_dpp v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf0,0x02,0x7f,0x02,0x77,0x39,0x05]
# GFX1250-REAL16: v_cvt_f16_bf8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf0,0x02,0x7f,0x02,0x77,0x39,0x05]
0xea,0xf0,0x02,0x7e,0x02,0x77,0x39,0x05
@@ -201,7 +201,7 @@
# GFX1250-REAL16: v_cvt_f16_fp8_dpp v1.l, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xee,0x02,0x7e,0x02,0x77,0x39,0x05]
0xe9,0xee,0x02,0x7f,0x02,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_cvt_f16_fp8_dpp v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xee,0x02,0x7f,0x02,0x77,0x39,0x05]
# GFX1250-REAL16: v_cvt_f16_fp8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xee,0x02,0x7f,0x02,0x77,0x39,0x05]
0xea,0xec,0x02,0x7e,0x02,0x77,0x39,0x05
@@ -229,7 +229,7 @@
# GFX1250-REAL16: v_sat_pk4_i4_i8_dpp v1.l, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xe6,0x02,0x7e,0x02,0x77,0x39,0x05]
0xe9,0xe6,0x02,0x7f,0x02,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_sat_pk4_i4_i8_dpp v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xe6,0x02,0x7f,0x02,0x77,0x39,0x05]
# GFX1250-REAL16: v_sat_pk4_i4_i8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xe6,0x02,0x7f,0x02,0x77,0x39,0x05]
0xe9,0xe8,0x02,0x7e,0x02,0x77,0x39,0x05
@@ -241,5 +241,5 @@
# GFX1250-REAL16: v_sat_pk4_u4_u8_dpp v1.l, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xe8,0x02,0x7e,0x02,0x77,0x39,0x05]
0xe9,0xe8,0x02,0x7f,0x02,0x77,0x39,0x05
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_sat_pk4_u4_u8_dpp v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xe8,0x02,0x7f,0x02,0x77,0x39,0x05]
# GFX1250-REAL16: v_sat_pk4_u4_u8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xe8,0x02,0x7f,0x02,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
index dc1da9a684cdb..12dd81d38891c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
@@ -103,11 +103,11 @@
# GFX12-REAL16: v_ceil_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xb8,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_ceil_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb8,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_ceil_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb8,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb8,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_ceil_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_ceil_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -293,11 +293,11 @@
# GFX12-REAL16: v_cos_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xc2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_cos_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_cos_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc2,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_cos_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_cos_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -445,7 +445,7 @@
# GFX12-REAL16: v_cvt_f16_f32_dpp v5.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x5f,0x01,0x01]
0xfa,0x14,0xfe,0x7f,0x7f,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v127, v183 ; encoding: [0x7f,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_cvt_f16_f32_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0x7f,0x6f,0x3d,0x30]
# GFX12-REAL16: v_cvt_f16_f32_dpp v127.h, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0x7f,0x6f,0x3d,0x30]
0xfa,0x14,0x0a,0x7e,0x81,0x60,0x01,0x13
@@ -453,7 +453,7 @@
# GFX12-REAL16: v_cvt_f16_f32_dpp v5.l, v129 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7e,0x81,0x60,0x01,0x13]
0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_cvt_f16_f32_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_cvt_f16_f32_dpp v127.h, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x14,0x0a,0x7e,0x01,0x60,0x01,0x13
@@ -521,11 +521,11 @@
# GFX12-REAL16: v_cvt_f16_i16_dpp v127.l, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa2,0xfe,0x7e,0x7f,0x6f,0x0d,0x30]
0xfa,0xa2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_cvt_f16_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_cvt_f16_i16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa2,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX12-FAKE16: v_cvt_f16_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX12-REAL16: v_cvt_f16_i16_dpp v127.h, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -585,11 +585,11 @@
# GFX12-REAL16: v_cvt_f16_u16_dpp v127.l, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa0,0xfe,0x7e,0x7f,0x6f,0x0d,0x30]
0xfa,0xa0,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_cvt_f16_u16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa0,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_cvt_f16_u16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa0,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa0,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX12-FAKE16: v_cvt_f16_u16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa0,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX12-REAL16: v_cvt_f16_u16_dpp v127.h, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa0,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1007,11 +1007,11 @@
# GFX12-REAL16: v_cvt_i16_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xa6,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_cvt_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa6,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_cvt_i16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa6,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa6,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_cvt_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_cvt_i16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1219,11 +1219,11 @@
# GFX12-REAL16: v_cvt_norm_i16_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xc6,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_cvt_norm_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc6,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_cvt_norm_i16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc6,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc6,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_cvt_norm_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_cvt_norm_i16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1283,11 +1283,11 @@
# GFX12-REAL16: v_cvt_norm_u16_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xc8,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_cvt_norm_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc8,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_cvt_norm_u16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc8,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc8,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_cvt_norm_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_cvt_norm_u16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1389,11 +1389,11 @@
# GFX12-REAL16: v_cvt_u16_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa4,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xa4,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_cvt_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa4,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_cvt_u16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa4,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa4,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_cvt_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_cvt_u16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1559,11 +1559,11 @@
# GFX12-REAL16: v_exp_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb0,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xb0,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_exp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb0,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_exp_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb0,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb0,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_exp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_exp_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1665,11 +1665,11 @@
# GFX12-REAL16: v_floor_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xb6,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_floor_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb6,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_floor_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb6,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb6,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_floor_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_floor_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb6,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1771,11 +1771,11 @@
# GFX12-REAL16: v_fract_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbe,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xbe,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_fract_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbe,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_fract_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbe,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xbe,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_fract_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbe,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_fract_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbe,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1877,11 +1877,11 @@
# GFX12-REAL16: v_frexp_exp_i16_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb4,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xb4,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_frexp_exp_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb4,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_frexp_exp_i16_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb4,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb4,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_frexp_exp_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_frexp_exp_i16_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb4,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -1983,11 +1983,11 @@
# GFX12-REAL16: v_frexp_mant_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xb2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_frexp_mant_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xb2,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_frexp_mant_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_frexp_mant_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2089,11 +2089,11 @@
# GFX12-REAL16: v_log_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xae,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xae,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_log_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xae,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_log_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xae,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xae,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_log_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xae,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_log_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xae,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2405,11 +2405,11 @@
# GFX12-REAL16: v_not_b16_dpp v127.l, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd2,0xfe,0x7e,0x7f,0x6f,0x0d,0x30]
0xfa,0xd2,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_not_b16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xd2,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_not_b16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xd2,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xd2,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX12-FAKE16: v_not_b16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX12-REAL16: v_not_b16_dpp v127.h, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd2,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2511,11 +2511,11 @@
# GFX12-REAL16: v_rcp_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xa8,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_rcp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa8,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_rcp_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa8,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xa8,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_rcp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_rcp_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa8,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2659,11 +2659,11 @@
# GFX12-REAL16: v_rndne_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbc,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xbc,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_rndne_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbc,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_rndne_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbc,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xbc,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_rndne_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbc,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_rndne_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbc,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2765,11 +2765,11 @@
# GFX12-REAL16: v_rsq_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xac,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xac,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_rsq_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xac,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_rsq_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xac,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xac,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_rsq_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xac,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_rsq_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xac,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2871,11 +2871,11 @@
# GFX12-REAL16: v_sat_pk_u8_i16_dpp v127.l, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7e,0xff,0x6f,0x0d,0x30]
0xfa,0xc4,0x0a,0x7f,0x01,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, s1, v176 ; encoding: [0x01,0x60,0x01,0x13]
+# GFX12-FAKE16: v_sat_pk_u8_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc4,0x0a,0x7f,0x01,0x60,0x01,0x13]
# GFX12-REAL16: v_sat_pk_u8_i16_dpp v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc4,0x0a,0x7f,0x01,0x60,0x01,0x13]
0xfa,0xc4,0xfe,0x7f,0xff,0x6f,0x0d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v6, v255, v183 ; encoding: [0xff,0x6f,0x0d,0x30]
+# GFX12-FAKE16: v_sat_pk_u8_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
# GFX12-REAL16: v_sat_pk_u8_i16_dpp v127.h, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -2935,11 +2935,11 @@
# GFX12-REAL16: v_sin_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_sin_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_sin_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_sin_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_sin_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -3041,11 +3041,11 @@
# GFX12-REAL16: v_sqrt_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xaa,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xaa,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_sqrt_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xaa,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_sqrt_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xaa,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xaa,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_sqrt_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xaa,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_sqrt_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xaa,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0xff
@@ -3147,11 +3147,11 @@
# GFX12-REAL16: v_trunc_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xba,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
0xfa,0xba,0x0a,0x7f,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_trunc_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xba,0x0a,0x7f,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_trunc_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xba,0x0a,0x7f,0x81,0x60,0x01,0x13]
0xfa,0xba,0xfe,0x7f,0xff,0x6f,0x3d,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-FAKE16: v_trunc_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xba,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
# GFX12-REAL16: v_trunc_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xba,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
index ead9278665c8d..cb5fa3839ace4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
@@ -21,11 +21,11 @@
# GFX12-REAL16: v_ceil_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_ceil_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_ceil_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_ceil_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_ceil_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -55,11 +55,11 @@
# GFX12-REAL16: v_cos_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_cos_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_cos_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cos_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cos_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x6c,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -95,11 +95,11 @@
# GFX12-REAL16: v_cvt_f16_f32_dpp v127.l, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x14,0xfe,0x7e,0xff,0x00,0x00,0x00]
0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05
+# GFX12-FAKE16: v_cvt_f16_f32_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05]
# GFX12-REAL16: v_cvt_f16_f32_dpp v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[1:2], v[187:188] ; encoding: [0x01,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[1:2]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x01,0x77,0x39,0x05]
0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cvt_f16_f32_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cvt_f16_f32_dpp v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xa2,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -111,11 +111,11 @@
# GFX12-REAL16: v_cvt_f16_i16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_cvt_f16_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_cvt_f16_i16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cvt_f16_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cvt_f16_i16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xa0,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -127,11 +127,11 @@
# GFX12-REAL16: v_cvt_f16_u16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_cvt_f16_u16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_cvt_f16_u16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cvt_f16_u16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cvt_f16_u16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -201,11 +201,11 @@
# GFX12-REAL16: v_cvt_i16_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_cvt_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_cvt_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cvt_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cvt_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x10,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -245,11 +245,11 @@
# GFX12-REAL16: v_cvt_norm_i16_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_cvt_norm_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_cvt_norm_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cvt_norm_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cvt_norm_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xc8,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -261,11 +261,11 @@
# GFX12-REAL16: v_cvt_norm_u16_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_cvt_norm_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_cvt_norm_u16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cvt_norm_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cvt_norm_u16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x1c,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -283,11 +283,11 @@
# GFX12-REAL16: v_cvt_u16_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa4,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_cvt_u16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_cvt_u16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_cvt_u16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_cvt_u16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x0e,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -321,11 +321,11 @@
# GFX12-REAL16: v_exp_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_exp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_exp_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_exp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_exp_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x4a,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -343,11 +343,11 @@
# GFX12-REAL16: v_floor_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_floor_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_floor_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_floor_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_floor_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x48,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -365,11 +365,11 @@
# GFX12-REAL16: v_fract_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbe,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_fract_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_fract_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_fract_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_fract_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x40,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -387,11 +387,11 @@
# GFX12-REAL16: v_frexp_exp_i16_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb4,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_frexp_exp_i16_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_frexp_exp_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_frexp_exp_i16_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_frexp_exp_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x7e,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -409,11 +409,11 @@
# GFX12-REAL16: v_frexp_mant_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_frexp_mant_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_frexp_mant_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_frexp_mant_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -431,11 +431,11 @@
# GFX12-REAL16: v_log_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xae,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_log_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_log_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_log_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_log_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x4e,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -483,11 +483,11 @@
# GFX12-REAL16: v_not_b16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_not_b16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_not_b16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_not_b16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_not_b16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00]
@@ -506,11 +506,11 @@
# GFX12-REAL16: v_rcp_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_rcp_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_rcp_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_rcp_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_rcp_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x54,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -534,11 +534,11 @@
# GFX12-REAL16: v_rndne_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbc,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_rndne_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_rndne_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_rndne_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_rndne_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x46,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -556,11 +556,11 @@
# GFX12-REAL16: v_rsq_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xac,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_rsq_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_rsq_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_rsq_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_rsq_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x5c,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -578,11 +578,11 @@
# GFX12-REAL16: v_sat_pk_u8_i16_dpp v127.l, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc4,0xfe,0x7e,0xff,0x00,0x00,0x00]
0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05
+# GFX12-FAKE16: v_sat_pk_u8_i16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05]
# GFX12-REAL16: v_sat_pk_u8_i16_dpp v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[1:2], v[187:188] ; encoding: [0x01,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[1:2]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x01,0x77,0x39,0x05]
0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_sat_pk_u8_i16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_sat_pk_u8_i16_dpp v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -594,11 +594,11 @@
# GFX12-REAL16: v_sin_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_sin_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_sin_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_sin_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_sin_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -616,11 +616,11 @@
# GFX12-REAL16: v_sqrt_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xaa,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_sqrt_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_sqrt_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_sqrt_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_sqrt_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x66,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -638,11 +638,11 @@
# GFX12-REAL16: v_trunc_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00]
0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_trunc_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_trunc_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05]
-# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
-# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05]
0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_trunc_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_trunc_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00]
0xe9,0x42,0x0a,0x7e,0x01,0x77,0x39,0x05
@@ -650,3 +650,6 @@
0xea,0x42,0xfe,0x7f,0xff,0x00,0x00,0x00
# GFX12: v_trunc_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x42,0xfe,0x7f,0xff,0x00,0x00,0x00]
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# GFX1200-FAKE16: {{.*}}
+# GFX1250-FAKE16: {{.*}}
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
index a393dd4554b78..887e4a856dd02 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
@@ -117,11 +117,11 @@
# GFX12-REAL16: v_add_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30]
0xfa,0x04,0x0b,0x65,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_add_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x65,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_add_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x65,0x81,0x60,0x01,0x13]
0xfa,0xfe,0xff,0x65,0xff,0x6f,0xfd,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX12-FAKE16: v_add_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x65,0xff,0x6f,0xfd,0x30]
# GFX12-REAL16: v_add_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x65,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff
@@ -447,11 +447,11 @@
# GFX12-REAL16: v_fmac_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30]
0xfa,0x04,0x0b,0x6d,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_fmac_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x6d,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_fmac_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x6d,0x81,0x60,0x01,0x13]
0xfa,0xfe,0xff,0x6d,0xff,0x6f,0xfd,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX12-FAKE16: v_fmac_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6d,0xff,0x6f,0xfd,0x30]
# GFX12-REAL16: v_fmac_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6d,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff
@@ -1463,11 +1463,11 @@
# GFX12-REAL16: v_sub_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30]
0xfa,0x04,0x0b,0x67,0x81,0x60,0x01,0x13
-# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-FAKE16: v_sub_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x67,0x81,0x60,0x01,0x13]
# GFX12-REAL16: v_sub_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x67,0x81,0x60,0x01,0x13]
0xfa,0xfe,0xff,0x67,0xff,0x6f,0xfd,0x30
-# GFX12-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX12-FAKE16: v_sub_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x67,0xff,0x6f,0xfd,0x30]
# GFX12-REAL16: v_sub_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x67,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
index 8972e3d936af8..3999073960587 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
@@ -21,10 +21,11 @@
# GFX12-REAL16: v_add_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00]
0xe9,0x04,0x0b,0x65,0x81,0x77,0x39,0x05
-# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-FAKE16: v_add_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x65,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_add_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x65,0x81,0x77,0x39,0x05]
0xea,0xfe,0xff,0x65,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_add_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x65,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_add_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x65,0xff,0x00,0x00,0x00]
0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05
@@ -74,10 +75,11 @@
# GFX12-REAL16: v_fmac_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00]
0xe9,0x04,0x0b,0x6d,0x81,0x77,0x39,0x05
-# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-FAKE16: v_fmac_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x6d,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_fmac_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x6d,0x81,0x77,0x39,0x05]
0xea,0xfe,0xff,0x6d,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_fmac_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x6d,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_fmac_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x6d,0xff,0x00,0x00,0x00]
0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05
@@ -225,10 +227,11 @@
# GFX12-REAL16: v_sub_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00]
0xe9,0x04,0x0b,0x67,0x81,0x77,0x39,0x05
-# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-FAKE16: v_sub_f16_dpp v133/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x67,0x81,0x77,0x39,0x05]
# GFX12-REAL16: v_sub_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x67,0x81,0x77,0x39,0x05]
0xea,0xfe,0xff,0x67,0xff,0x00,0x00,0x00
+# GFX12-FAKE16: v_sub_f16_dpp v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x67,0xff,0x00,0x00,0x00]
# GFX12-REAL16: v_sub_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x67,0xff,0x00,0x00,0x00]
0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05
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