[llvm] [LV][EVL] Add test case for checking debug info when tail folding by EVL. nfc (PR #172429)
Mel Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 17 00:25:00 PST 2025
================
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize \
+; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \
+; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+
+define void @reverse_store(ptr %a, i64 %n) !dbg !4 {
+; CHECK-LABEL: define void @reverse_store(
+; CHECK-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG4:![0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: #dbg_value(ptr [[A]], [[META11:![0-9]+]], !DIExpression(), [[META15:![0-9]+]])
+; CHECK-NEXT: #dbg_value(i64 [[N]], [[META12:![0-9]+]], !DIExpression(), [[META15]])
+; CHECK-NEXT: #dbg_value(i64 [[N]], [[META13:![0-9]+]], !DIExpression(DW_OP_constu, 1, DW_OP_minus, DW_OP_stack_value), [[META16:![0-9]+]])
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1, !dbg [[DBG17:![0-9]+]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1), !dbg [[DBG17]]
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[UMIN]], !dbg [[DBG17]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]], !dbg [[DBG17]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[N]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = mul nsw <vscale x 4 x i64> [[TMP2]], splat (i64 -1)
+; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw <vscale x 4 x i64> [[BROADCAST_SPLAT]], [[TMP3]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]], !dbg [[DBG17]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP1]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
+; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
+; CHECK-NEXT: [[TMP6:%.*]] = mul nsw i64 -1, [[TMP5]]
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP6]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT1]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP7:%.*]] = add nsw <vscale x 4 x i64> [[VEC_IND]], splat (i64 -1), !dbg [[DBG18:![0-9]+]]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 4 x i64> [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[TMP8]], !dbg [[DBG19:![0-9]+]]
+; CHECK-NEXT: [[TMP10:%.*]] = trunc nuw nsw <vscale x 4 x i64> [[TMP7]] to <vscale x 4 x i32>, !dbg [[DBG21:![0-9]+]]
+; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP4]] to i64, !dbg [[DBG21]]
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 0, [[TMP11]], !dbg [[DBG21]]
+; CHECK-NEXT: [[TMP13:%.*]] = sub i64 [[TMP11]], 1, !dbg [[DBG21]]
+; CHECK-NEXT: [[TMP14:%.*]] = mul i64 -1, [[TMP13]], !dbg [[DBG21]]
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP9]], i64 [[TMP12]], !dbg [[DBG21]]
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP15]], i64 [[TMP14]], !dbg [[DBG21]]
+; CHECK-NEXT: [[VP_REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[TMP10]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG21]]
+; CHECK-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_REVERSE]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG21]]
+; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT2]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
+; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[FOR_COND_CLEANUP:.*]]
+; CHECK: [[FOR_COND_CLEANUP]]:
+; CHECK-NEXT: ret void, !dbg [[DBG25:![0-9]+]]
+;
+entry:
+ #dbg_value(ptr %a, !11, !DIExpression(), !15)
+ #dbg_value(i64 %n, !12, !DIExpression(), !15)
+ #dbg_value(i64 %n, !13, !DIExpression(DW_OP_constu, 1, DW_OP_minus, DW_OP_stack_value), !16)
+ br label %for.body, !dbg !17
+
+for.cond.cleanup: ; preds = %for.body
+ ret void, !dbg !18
+
+for.body: ; preds = %entry, %for.body
+ %indvars.iv = phi i64 [ %n, %entry ], [ %indvars.iv.next, %for.body ]
+ #dbg_value(i64 %indvars.iv, !13, !DIExpression(DW_OP_constu, 1, DW_OP_minus, DW_OP_stack_value), !16)
+ %indvars.iv.next = add nsw i64 %indvars.iv, -1, !dbg !20
+ #dbg_value(i64 %indvars.iv.next, !13, !DIExpression(), !16)
+ %arrayidx = getelementptr inbounds nuw i32, ptr %a, i64 %indvars.iv.next, !dbg !21
+ %1 = trunc nuw nsw i64 %indvars.iv.next to i32, !dbg !22
+ store i32 %1, ptr %arrayidx, align 4, !dbg !22
+ #dbg_value(i64 %indvars.iv.next, !13, !DIExpression(DW_OP_constu, 1, DW_OP_minus, DW_OP_stack_value), !16)
+ %cmp = icmp samesign ugt i64 %indvars.iv, 1, !dbg !23
+ br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !24, !llvm.loop !25
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "dbg-tail-folding-by-evl.cpp", directory: "/test/file/path")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !{i32 7, !"debug-info-assignment-tracking", i1 true}
+!4 = distinct !DISubprogram(name: "reverse_store", linkageName: "_Z13reverse_storePil", scope: !1, file: !1, line: 1, type: !5, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !10)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null, !7, !8}
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64)
+!8 = !DIBasicType(name: "long", size: 64, encoding: DW_ATE_signed)
+!9 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
----------------
Mel-Chen wrote:
Cleared most of the metadata, thanks.
https://github.com/llvm/llvm-project/pull/172429
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