[llvm] [RISC-V] Add schedule information for Qualcomm extensions (PR #172601)

[Sam Elliott via llvm-commits]

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@@ -948,11 +959,13 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   def QC_CLO : QCIRVInstI<0b0100, "qc.clo">;
   def QC_CTO : QCIRVInstI<0b0101, "qc.cto">;
   def QC_BREV32 : QCIRVInstI<0b0110, "qc.brev32">;
-  def QC_C_BEXTI  : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">;
-  def QC_C_BSETI  : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">;
+  def QC_C_BEXTI  : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">,
+                    Sched<[WriteIALU, ReadIALU]>;
+  def QC_C_BSETI  : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">, Sched<[WriteIALU]>;
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lenary wrote:

I think this is missing a `ReadIALU`

https://github.com/llvm/llvm-project/pull/172601