[llvm] SelectionDAG: Improve expandFMINIMUM_FMAXIMUM (PR #137367)

[Phoebe Wang via llvm-commits]

================
@@ -8745,54 +8767,66 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
   // First, implement comparison not propagating NaN. If no native fmin or fmax
   // available, use plain select with setcc instead.
   SDValue MinMax;
-  unsigned CompOpcIeee = IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
-  unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM;
-
-  // FIXME: We should probably define fminnum/fmaxnum variants with correct
-  // signed zero behavior.
-  bool MinMaxMustRespectOrderedZero = false;
-
-  if (isOperationLegalOrCustom(CompOpcIeee, VT)) {
-    MinMax = DAG.getNode(CompOpcIeee, DL, VT, LHS, RHS, Flags);
-    MinMaxMustRespectOrderedZero = true;
-  } else if (isOperationLegalOrCustom(CompOpc, VT)) {
-    MinMax = DAG.getNode(CompOpc, DL, VT, LHS, RHS, Flags);
+  unsigned MinMaxOpcIeee = IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
+  unsigned MinMaxOpcNum = IsMax ? ISD::FMAXNUM : ISD::FMINNUM;
+  unsigned MinMaxOpcNum2019 = IsMax ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
+  unsigned MinMaxOpc = ISD::DELETED_NODE;
+
+  bool IsZeroOrdered = true;
+
+  if (isOperationLegal(MinMaxOpcIeee, VT))
+    MinMaxOpc = MinMaxOpcIeee;
+  else if (isOperationLegal(MinMaxOpcNum, VT))
+    MinMaxOpc = MinMaxOpcNum;
+  else if (isOperationLegal(MinMaxOpcNum2019, VT))
+    MinMaxOpc = MinMaxOpcNum2019;
+  else if (isOperationCustom(MinMaxOpcIeee, VT))
+    MinMaxOpc = MinMaxOpcIeee;
+  else if (isOperationCustom(MinMaxOpcNum2019, VT))
+    MinMaxOpc = MinMaxOpcNum2019;
+  // TODO: we don't use isOperationCustom(ISD::FMAXNUM or ISD::FMINNUM)
+  // due to some backends cannot process +0 vs -0 correctly: x86 is an
+  // example.
+  if (MinMaxOpc != ISD::DELETED_NODE) {
+    // TODO: we can also move NaN from RHS to LHS
+    // and LHS to RHS, so that we can keep payloads of NaNs.
+    //
+    MinMax = DAG.getNode(MinMaxOpc, DL, VT, LHS, RHS, Flags);
+    if (!N->getFlags().hasNoNaNs() &&
+        (!DAG.isKnownNeverNaN(RHS) || !DAG.isKnownNeverNaN(LHS))) {
+      ConstantFP *FPNaN = ConstantFP::get(
+          *DAG.getContext(), APFloat::getNaN(VT.getFltSemantics()));
+      MinMax =
+          DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, LHS, RHS, ISD::SETUO),
+                        DAG.getConstantFP(*FPNaN, DL, VT), MinMax, Flags);
+    }
   } else {
     if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))
       return DAG.UnrollVectorOp(N);
 
-    // NaN (if exists) will be propagated later, so orderness doesn't matter.
-    SDValue Compare =
-        DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETOGT : ISD::SETOLT);
-    MinMax = DAG.getSelect(DL, VT, Compare, LHS, RHS, Flags);
+    if (!Flags.hasNoNaNs() && !DAG.isKnownNeverNaN(RHS))
+      LHS = DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, RHS, RHS, ISD::SETUO),
+                          RHS, LHS, Flags);
+    MinMax = DAG.getSelectCC(DL, LHS, RHS, LHS, RHS,
+                             IsMax ? ISD::SETUGT : ISD::SETULT);
+    IsZeroOrdered = false;
   }
 
-  // Propagate any NaN of both operands
-  if (!N->getFlags().hasNoNaNs() &&
-      (!DAG.isKnownNeverNaN(RHS) || !DAG.isKnownNeverNaN(LHS))) {
-    ConstantFP *FPNaN = ConstantFP::get(*DAG.getContext(),
-                                        APFloat::getNaN(VT.getFltSemantics()));
-    MinMax = DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, LHS, RHS, ISD::SETUO),
-                           DAG.getConstantFP(*FPNaN, DL, VT), MinMax, Flags);
-  }
+  // TODO: We need quiet sNaN if strictfp.
----------------
phoebewang wrote:

My prior question was about sNaN. So the solution is agian a TODO?

I think it's more important for Rust once it's changed to use `minimumnum/maximumnum + nsz`. @RalfJung 

https://github.com/llvm/llvm-project/pull/137367