[llvm] [MachineVerifier](NFC)(TestOnly) Canonicalise top-level MachineVerifier tests (PR #172527)
Nathan Corbyn via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 16 10:11:19 PST 2025
https://github.com/cofibrant created https://github.com/llvm/llvm-project/pull/172527
None
>From a87a01d4daf3fc763f26f8287afc59ecca64b73a Mon Sep 17 00:00:00 2001
From: Nathan Corbyn <n_corbyn at apple.com>
Date: Tue, 16 Dec 2025 18:10:04 +0000
Subject: [PATCH] [MachineVerifier](NFC)(TestOnly) Canonicalise top-level
MachineVerifier tests
---
llvm/test/MachineVerifier/copy-scalable.mir | 23 +++--------
.../generic-vreg-undef-use.mir | 13 +++----
llvm/test/MachineVerifier/live-ins-01.mir | 17 ++++-----
llvm/test/MachineVerifier/live-ins-02.mir | 10 ++---
llvm/test/MachineVerifier/live-ins-03.mir | 10 ++---
.../stack-protector-offset.mir | 6 +--
llvm/test/MachineVerifier/test_abd_su.mir | 6 +--
.../MachineVerifier/test_adjustsstack.mir | 6 +--
llvm/test/MachineVerifier/test_copy.mir | 9 +++--
.../test_copy_mismatch_types.mir | 10 ++---
.../test_copy_physregs_x86.mir | 15 ++++----
llvm/test/MachineVerifier/test_g_add.mir | 12 ++----
.../MachineVerifier/test_g_addrspacecast.mir | 12 ++----
.../MachineVerifier/test_g_assert_align.mir | 12 ++----
.../MachineVerifier/test_g_assert_sext.mir | 22 ++++++-----
...test_g_assert_sext_register_bank_class.mir | 18 ++++-----
.../MachineVerifier/test_g_assert_zext.mir | 22 ++++++-----
...test_g_assert_zext_register_bank_class.mir | 21 +++++-----
.../test_g_brindirect_is_indirect_branch.mir | 9 ++---
llvm/test/MachineVerifier/test_g_brjt.mir | 15 ++++----
.../test_g_brjt_is_indirect_branch.mir | 15 +++-----
llvm/test/MachineVerifier/test_g_bswap.mir | 12 ++----
.../MachineVerifier/test_g_build_vector.mir | 9 ++---
.../test_g_build_vector_trunc.mir | 12 ++----
llvm/test/MachineVerifier/test_g_bzero.mir | 26 ++++++-------
.../MachineVerifier/test_g_concat_vectors.mir | 15 +++-----
llvm/test/MachineVerifier/test_g_constant.mir | 12 ++----
.../MachineVerifier/test_g_constant_pool.mir | 16 +++-----
.../MachineVerifier/test_g_dyn_stackalloc.mir | 8 ++--
llvm/test/MachineVerifier/test_g_extract.mir | 12 ++----
.../test_g_extract_subvector.mir | 10 ++---
llvm/test/MachineVerifier/test_g_fcmp.mir | 14 ++-----
.../test/MachineVerifier/test_g_fconstant.mir | 12 ++----
llvm/test/MachineVerifier/test_g_icmp.mir | 18 +++------
llvm/test/MachineVerifier/test_g_insert.mir | 10 ++---
.../test_g_insert_subvector.mir | 8 ++--
llvm/test/MachineVerifier/test_g_inttoptr.mir | 12 ++----
.../test_g_invoke_region_start.mir | 12 ++----
.../MachineVerifier/test_g_is_fpclass.mir | 1 -
.../MachineVerifier/test_g_jump_table.mir | 16 +++-----
llvm/test/MachineVerifier/test_g_llround.mir | 12 ++----
llvm/test/MachineVerifier/test_g_load.mir | 12 ++----
llvm/test/MachineVerifier/test_g_lround.mir | 12 ++----
llvm/test/MachineVerifier/test_g_memcpy.mir | 12 ++----
.../MachineVerifier/test_g_memcpy_inline.mir | 12 ++----
llvm/test/MachineVerifier/test_g_memmove.mir | 38 +++++++++----------
llvm/test/MachineVerifier/test_g_memset.mir | 25 +++++-------
.../MachineVerifier/test_g_merge_values.mir | 10 ++---
llvm/test/MachineVerifier/test_g_phi.mir | 34 +++++++----------
llvm/test/MachineVerifier/test_g_prefetch.mir | 19 ++++------
llvm/test/MachineVerifier/test_g_ptr_add.mir | 11 ++----
llvm/test/MachineVerifier/test_g_ptrmask.mir | 9 ++---
llvm/test/MachineVerifier/test_g_ptrtoint.mir | 12 ++----
.../test/MachineVerifier/test_g_rotr_rotl.mir | 6 +--
llvm/test/MachineVerifier/test_g_select.mir | 12 ++----
.../MachineVerifier/test_g_sext_inreg.mir | 16 ++++----
llvm/test/MachineVerifier/test_g_sextload.mir | 14 ++-----
llvm/test/MachineVerifier/test_g_shift.mir | 2 +-
.../MachineVerifier/test_g_shuffle_vector.mir | 10 ++---
.../MachineVerifier/test_g_splat_vector.mir | 9 ++---
llvm/test/MachineVerifier/test_g_store.mir | 12 ++----
llvm/test/MachineVerifier/test_g_trunc.mir | 12 ++----
.../test/MachineVerifier/test_g_ubfx_sbfx.mir | 8 ++--
.../test/MachineVerifier/test_g_ubsantrap.mir | 9 ++---
.../MachineVerifier/test_g_unmerge_values.mir | 2 +-
llvm/test/MachineVerifier/test_g_vscale.mir | 15 ++++----
llvm/test/MachineVerifier/test_g_zextload.mir | 14 ++-----
.../MachineVerifier/test_insert_subreg.mir | 20 ++++------
.../MachineVerifier/test_multiple_errors.mir | 14 +++----
.../test_phis_precede_nonphis.mir | 6 +--
.../test/MachineVerifier/test_step-vector.mir | 6 +--
llvm/test/MachineVerifier/test_uscmp.mir | 8 ++--
.../test_vector_reductions.mir | 12 ++----
.../verifier-generic-extend-truncate.mir | 9 ++---
.../verifier-generic-types-1.mir | 7 ++--
.../verifier-generic-types-2.mir | 7 ++--
.../MachineVerifier/verifier-phi-fail0.mir | 2 +-
llvm/test/MachineVerifier/verifier-phi.mir | 2 +-
.../MachineVerifier/verifier-statepoint.mir | 2 +-
.../MachineVerifier/verify-inlineasmbr.mir | 5 +--
.../verify-regbankselected-dbg-undef-use.mir | 2 +-
.../verify-regbankselected.mir | 4 +-
llvm/test/MachineVerifier/verify-regops.mir | 11 +++---
.../verify-selected-dbg-undef-use.mir | 2 +-
llvm/test/MachineVerifier/verify-selected.mir | 4 +-
85 files changed, 383 insertions(+), 617 deletions(-)
diff --git a/llvm/test/MachineVerifier/copy-scalable.mir b/llvm/test/MachineVerifier/copy-scalable.mir
index 28d3e71245501..7f96cdaa90043 100644
--- a/llvm/test/MachineVerifier/copy-scalable.mir
+++ b/llvm/test/MachineVerifier/copy-scalable.mir
@@ -1,13 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv64 -o - -global-isel -run-pass=none -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -o - -global-isel -run-pass=none %s | FileCheck %s
# REQUIRES: riscv64-registered-target
---
-name: test_copy_physical_to_virtual_nxv1s8
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
+name: test_copy_physical_to_virtual_nxv1s8
registers:
- { id: 0, class: _, preferred-register: '' }
liveins:
@@ -23,10 +19,8 @@ body: |
...
---
-name: test_copy_physical_to_virtual_nxv16s8
-legalized: true
-tracksRegLiveness: true
-body: |
+name: test_copy_physical_to_virtual_nxv16s8
+body: |
bb.1.entry:
liveins: $v8
; CHECK-LABEL: name: test_copy_physical_to_virtual_nxv16s8
@@ -38,15 +32,10 @@ body: |
...
---
-name: test_copy_virtual_to_physical
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
+name: test_copy_virtual_to_physical
registers:
- { id: 0, class: _, preferred-register: '' }
-liveins:
-body: |
+body: |
bb.0:
liveins: $v8
diff --git a/llvm/test/MachineVerifier/generic-vreg-undef-use.mir b/llvm/test/MachineVerifier/generic-vreg-undef-use.mir
index aa755ab339f07..fcc31e4e830da 100644
--- a/llvm/test/MachineVerifier/generic-vreg-undef-use.mir
+++ b/llvm/test/MachineVerifier/generic-vreg-undef-use.mir
@@ -1,25 +1,24 @@
-# RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
# Undef uses are illegal for generic vregs.
---
-name: test_undef_use
-liveins:
-body: |
+name: test_undef_use
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
; Test generic instruction
- ; CHECK: *** Bad machine code: Generic virtual register use cannot be undef ***
+ ; CHECK: Bad machine code: Generic virtual register use cannot be undef
G_STORE %0, undef %1:_(p0) :: (store (s32))
; Make sure this fails on a post-isel generic instruction.
- ; CHECK: *** Bad machine code: Generic virtual register use cannot be undef ***
+ ; CHECK: Bad machine code: Generic virtual register use cannot be undef
$x0 = COPY undef %2:_(s64)
; Make sure this fails with a target instruction
- ; CHECK: *** Bad machine code: Generic virtual register use cannot be undef ***
+ ; CHECK: Bad machine code: Generic virtual register use cannot be undef
RET_ReallyLR implicit $x0, implicit undef %3:_(s32)
...
diff --git a/llvm/test/MachineVerifier/live-ins-01.mir b/llvm/test/MachineVerifier/live-ins-01.mir
index 5d6d2fa399e78..1d9af60610a17 100644
--- a/llvm/test/MachineVerifier/live-ins-01.mir
+++ b/llvm/test/MachineVerifier/live-ins-01.mir
@@ -1,17 +1,17 @@
-# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: systemz-registered-target
# Test that a the machine verifier reports an error when a register in
# liveins is not liveout from predecessor.
---
-name: f1
+name: f1
tracksRegLiveness: true
machineFunctionInfo: {}
-body: |
+body: |
bb.0:
liveins: $r2l, $r3l
-
+
%1:gr32bit = COPY $r3l
%0:gr32bit = COPY $r2l
CHIMux %0, 0, implicit-def $cc
@@ -27,18 +27,18 @@ body: |
Return implicit $r2l
...
-# CHECK: *** Bad machine code: Live in register not found to be live out from predecessor. ***
+# CHECK: Bad machine code: Live in register not found to be live out from predecessor
# CHECK:- function: f2
# CHECK:- basic block: %bb.2
# CHECK:CC not found to be live out from %bb.1
---
-name: f2
+name: f2
tracksRegLiveness: true
machineFunctionInfo: {}
-body: |
+body: |
bb.0:
liveins: $r2l, $r3l
-
+
%1:gr32bit = COPY $r3l
%0:gr32bit = COPY $r2l
CHIMux %0, 0, implicit-def $cc
@@ -53,5 +53,4 @@ body: |
%2:grx32bit = LOCRMux %1, %0, 14, 8, implicit $cc
$r2l = COPY %2
Return implicit $r2l
-
...
diff --git a/llvm/test/MachineVerifier/live-ins-02.mir b/llvm/test/MachineVerifier/live-ins-02.mir
index 2cc63ac0cd212..6b9447e1f01ce 100644
--- a/llvm/test/MachineVerifier/live-ins-02.mir
+++ b/llvm/test/MachineVerifier/live-ins-02.mir
@@ -1,17 +1,17 @@
-# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: systemz-registered-target
# Test that a the machine verifier reports an error when a register in
# liveins is not liveout from predecessor.
---
-name: f1
+name: f1
tracksRegLiveness: true
machineFunctionInfo: {}
-body: |
+body: |
bb.0:
liveins: $r2l, $r3l
-
+
%1:gr32bit = COPY $r3l
%0:gr32bit = COPY $r2l
CHIMux %0, 0, implicit-def $cc
@@ -26,7 +26,7 @@ body: |
Return implicit $r2l
...
-# CHECK: *** Bad machine code: Live in register not found to be live out from predecessor. ***
+# CHECK: Bad machine code: Live in register not found to be live out from predecessor
# CHECK:- function: f1
# CHECK:- basic block: %bb.2
# CHECK:CC not found to be live out from %bb.1
diff --git a/llvm/test/MachineVerifier/live-ins-03.mir b/llvm/test/MachineVerifier/live-ins-03.mir
index ae640c439d3e1..1b2cc9fb53b3c 100644
--- a/llvm/test/MachineVerifier/live-ins-03.mir
+++ b/llvm/test/MachineVerifier/live-ins-03.mir
@@ -1,17 +1,17 @@
-# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: systemz-registered-target
# Test that a the machine verifier reports an error when a register in
# liveins is not liveout from predecessor.
---
-name: f1
+name: f1
tracksRegLiveness: true
machineFunctionInfo: {}
-body: |
+body: |
bb.0:
liveins: $r2l, $r3l
-
+
%1:gr32bit = COPY $r3l
%0:gr32bit = COPY $r2l
CHIMux %0, 0, implicit-def $cc
@@ -30,7 +30,7 @@ body: |
Return implicit $r2l
...
-# CHECK: *** Bad machine code: Live in register not found to be live out from predecessor. ***
+# CHECK: Bad machine code: Live in register not found to be live out from predecessor
# CHECK:- function: f1
# CHECK:- basic block: %bb.3
# CHECK:CC not found to be live out from %bb.2
diff --git a/llvm/test/MachineVerifier/stack-protector-offset.mir b/llvm/test/MachineVerifier/stack-protector-offset.mir
index 47008e1b12354..16ee3c8da8979 100644
--- a/llvm/test/MachineVerifier/stack-protector-offset.mir
+++ b/llvm/test/MachineVerifier/stack-protector-offset.mir
@@ -21,7 +21,7 @@ body: |
...
;--- lower.mir
-# CHECK: *** Bad machine code: Stack protector is not the top-most object on the stack ***
+# CHECK: Bad machine code: Stack protector is not the top-most object on the stack
---
name: lower
frameInfo:
@@ -35,7 +35,7 @@ body: |
...
;--- overlap.mir
-# CHECK: *** Bad machine code: Stack protector overlaps with another stack object ***
+# CHECK: Bad machine code: Stack protector overlaps with another stack object
---
name: overlap
frameInfo:
@@ -49,7 +49,7 @@ body: |
...
;--- higher.mir
-# CHECK: *** Bad machine code: Stack protector is not the top-most object on the stack ***
+# CHECK: Bad machine code: Stack protector is not the top-most object on the stack
---
name: higher
frameInfo:
diff --git a/llvm/test/MachineVerifier/test_abd_su.mir b/llvm/test/MachineVerifier/test_abd_su.mir
index 992f58c506029..a43a3dc28a564 100644
--- a/llvm/test/MachineVerifier/test_abd_su.mir
+++ b/llvm/test/MachineVerifier/test_abd_su.mir
@@ -1,8 +1,8 @@
-# RUN: not --crash llc -verify-machineinstrs -mtriple=arm64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: g_abd_su
+name: g_abd_su
body: |
bb.0:
@@ -35,6 +35,4 @@ body: |
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
%20:_(s1) = G_ABDU %18, %19
-
...
-
diff --git a/llvm/test/MachineVerifier/test_adjustsstack.mir b/llvm/test/MachineVerifier/test_adjustsstack.mir
index d333737e000cc..cddcd452bef8a 100644
--- a/llvm/test/MachineVerifier/test_adjustsstack.mir
+++ b/llvm/test/MachineVerifier/test_adjustsstack.mir
@@ -1,6 +1,6 @@
-# RUN: not --crash llc -o - -start-before=twoaddressinstruction -verify-machineinstrs %s 2>&1 \
-# RUN: | FileCheck %s
+# RUN: not --crash llc -start-before=twoaddressinstruction -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
--- |
target triple = "aarch64-unknown-linux"
declare i32 @bar(i32) nounwind
@@ -23,4 +23,4 @@ body: |
$w0 = COPY killed %0
RET_ReallyLR implicit $w0
...
-# CHECK-LABEL: Bad machine code: AdjustsStack not set in presence of a frame pseudo instruction.
+# CHECK-LABEL: Bad machine code: AdjustsStack not set in presence of a frame pseudo instruction
diff --git a/llvm/test/MachineVerifier/test_copy.mir b/llvm/test/MachineVerifier/test_copy.mir
index 9b96902880a2b..0d521f8b6dfdc 100644
--- a/llvm/test/MachineVerifier/test_copy.mir
+++ b/llvm/test/MachineVerifier/test_copy.mir
@@ -1,11 +1,12 @@
-#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
--- |
; ModuleID = 'test.ll'
source_filename = "test.ll"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown"
-
+
define i32 @test_copy(i32 %argc) {
ret i32 0
}
@@ -20,9 +21,9 @@ legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
-registers:
+registers:
- { id: 0, class: _, preferred-register: '' }
-liveins:
+liveins:
body: |
bb.0:
liveins: $w0
diff --git a/llvm/test/MachineVerifier/test_copy_mismatch_types.mir b/llvm/test/MachineVerifier/test_copy_mismatch_types.mir
index 0fe1622f4cac6..836f3d4424100 100644
--- a/llvm/test/MachineVerifier/test_copy_mismatch_types.mir
+++ b/llvm/test/MachineVerifier/test_copy_mismatch_types.mir
@@ -1,15 +1,15 @@
-#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
--- |
; ModuleID = 'test.ll'
source_filename = "test.ll"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown"
-
+
define i32 @test_copy(i32 %argc) {
ret i32 0
}
-
...
---
name: test_copy
@@ -17,9 +17,9 @@ legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
-registers:
+registers:
- { id: 0, class: _, preferred-register: '' }
-liveins:
+liveins:
body: |
bb.0:
liveins: $w0
diff --git a/llvm/test/MachineVerifier/test_copy_physregs_x86.mir b/llvm/test/MachineVerifier/test_copy_physregs_x86.mir
index f3323c4353142..39d7934cc9ee8 100644
--- a/llvm/test/MachineVerifier/test_copy_physregs_x86.mir
+++ b/llvm/test/MachineVerifier/test_copy_physregs_x86.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=x86_64 -run-pass=none -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -implicit-check-not="Bad machine code"
+# RUN: not --crash llc -mtriple=x86_64 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s -implicit-check-not="Bad machine code"
# REQUIRES: x86-registered-target
# These copies have mismatched type sizes that are allowed because the
@@ -20,7 +20,6 @@ body: |
$xmm3 = COPY %3
$xmm4 = COPY %4
...
-
---
name: test_invalid_copies
tracksRegLiveness: true
@@ -28,27 +27,27 @@ body: |
bb.0:
liveins: $xmm0, $xmm1, $xmm2, $xmm3
- ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes ***
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
; CHECK: - instruction: %0:_(<4 x s16>) = COPY $xmm1
%0:_(<4 x s16>) = COPY $xmm1
- ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes ***
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
; CHECK: - instruction: %1:_(s256) = COPY $xmm2
%1:_(s256) = COPY $xmm2
- ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes ***
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
; CHECK: - instruction: %2:_(<8 x s32>) = COPY $xmm3
%2:_(<8 x s32>) = COPY $xmm3
- ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes ***
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
; CHECK: - instruction: $xmm1 = COPY %0:_(<4 x s16>)
$xmm1 = COPY %0
- ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes ***
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
; CHECK: - instruction: $xmm2 = COPY %1:_(s256)
$xmm2 = COPY %1
- ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes ***
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
; CHECK: - instruction: $xmm3 = COPY %2:_(<8 x s32>)
$xmm3 = COPY %2
...
diff --git a/llvm/test/MachineVerifier/test_g_add.mir b/llvm/test/MachineVerifier/test_g_add.mir
index cf07d315095f1..73062e12b00bb 100644
--- a/llvm/test/MachineVerifier/test_g_add.mir
+++ b/llvm/test/MachineVerifier/test_g_add.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -mtriple=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_add
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_add
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
@@ -33,5 +28,4 @@ body: |
; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: Bad machine code: Generic virtual register does not allow subregister index
%8:_(s32) = G_ADD %6.sub_32:_(s64), %0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_addrspacecast.mir b/llvm/test/MachineVerifier/test_g_addrspacecast.mir
index e1613883c5705..d5eb974592f76 100644
--- a/llvm/test/MachineVerifier/test_g_addrspacecast.mir
+++ b/llvm/test/MachineVerifier/test_g_addrspacecast.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_addrspacecast
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_addrspacecast
+body: |
bb.0:
%0:_(s64) = G_IMPLICIT_DEF
@@ -53,5 +48,4 @@ body: |
; CHECK: Bad machine code: addrspacecast must convert different address spaces
%15:_(<2 x p0>) = G_ADDRSPACE_CAST %3
-
...
diff --git a/llvm/test/MachineVerifier/test_g_assert_align.mir b/llvm/test/MachineVerifier/test_g_assert_align.mir
index 47bdc77d6ddf5..d449ac2bc4215 100644
--- a/llvm/test/MachineVerifier/test_g_assert_align.mir
+++ b/llvm/test/MachineVerifier/test_g_assert_align.mir
@@ -1,17 +1,13 @@
-#RUN: not --crash llc -mtriple=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_assert_align
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_assert_align
+body: |
bb.0:
liveins: $x0, $q0
%ptr:_(p0) = COPY $x0
; CHECK: Bad machine code: alignment immediate must be >= 1
%v:_(s32) = G_ASSERT_ALIGN %ptr:_(p0), 0
+...
diff --git a/llvm/test/MachineVerifier/test_g_assert_sext.mir b/llvm/test/MachineVerifier/test_g_assert_sext.mir
index 71127b59f8359..736aec00df2d4 100644
--- a/llvm/test/MachineVerifier/test_g_assert_sext.mir
+++ b/llvm/test/MachineVerifier/test_g_assert_sext.mir
@@ -1,7 +1,8 @@
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
-# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-name: test
+---
+name: test
body: |
bb.0:
liveins: $x0, $w0
@@ -9,34 +10,35 @@ body: |
%1:_(<4 x s16>) = COPY $x0
%2:_(s32) = COPY $w0
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT expects an immediate operand #2
; CHECK: instruction: %assert_sext_1:_(s64) = G_ASSERT_SEXT
%assert_sext_1:_(s64) = G_ASSERT_SEXT %0, %0
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT expects an immediate operand #2
; CHECK: instruction: %assert_sext_2:_(s64) = G_ASSERT_SEXT
%assert_sext_2:_(s64) = G_ASSERT_SEXT %0, i8 8
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT
%assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT %0, 8
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT
%assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT %1, 8
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be >= 1 ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT size must be >= 1
; CHECK: instruction: %assert_sext_5:_(s64) = G_ASSERT_SEXT
%assert_sext_5:_(s64) = G_ASSERT_SEXT %0, 0
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be less than source bit width ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT size must be less than source bit width
; CHECK: instruction: %assert_sext_6:_(s64) = G_ASSERT_SEXT
%assert_sext_6:_(s64) = G_ASSERT_SEXT %0, 128
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %assert_sext_7:_(s64) = G_ASSERT_SEXT %2:_, 8
%assert_sext_7:_(s64) = G_ASSERT_SEXT %2, 8
- ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
+ ; CHECK: Bad machine code: Generic instruction cannot have physical register
; CHECK: instruction: %assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8
%assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8
+...
diff --git a/llvm/test/MachineVerifier/test_g_assert_sext_register_bank_class.mir b/llvm/test/MachineVerifier/test_g_assert_sext_register_bank_class.mir
index 7dcb5ff1e9593..7e0d6ade5b873 100644
--- a/llvm/test/MachineVerifier/test_g_assert_sext_register_bank_class.mir
+++ b/llvm/test/MachineVerifier/test_g_assert_sext_register_bank_class.mir
@@ -1,31 +1,31 @@
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
-# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-name: test
-legalized: true
-regBankSelected: false
+---
+name: test
body: |
bb.0:
liveins: $w0, $w1
%bank:gpr(s32) = COPY $w0
%class:gpr32(s32) = COPY $w1
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT cannot change register bank ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT cannot change register bank
; CHECK: instruction: %bank_mismatch:fpr(s32) = G_ASSERT_SEXT %bank:gpr, 16
%bank_mismatch:fpr(s32) = G_ASSERT_SEXT %bank, 16
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register classes must match ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT source and destination register classes must match
; CHECK: instruction: %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_SEXT %class:gpr32, 16
%class_mismatch_gpr:gpr32all(s32) = G_ASSERT_SEXT %class, 16
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT cannot change register bank ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT cannot change register bank
; CHECK: instruction: %class_mismatch_fpr:fpr32(s32) = G_ASSERT_SEXT %class:gpr32, 16
%class_mismatch_fpr:fpr32(s32) = G_ASSERT_SEXT %class, 16
- ; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register classes must match ***
+ ; CHECK: Bad machine code: G_ASSERT_SEXT source and destination register classes must match
; CHECK: instruction: %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_SEXT %bank:gpr, 16
%dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_SEXT %bank, 16
- ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
+ ; CHECK: Bad machine code: Generic instruction cannot have physical register
; CHECK: instruction: %implicit_physreg:gpr(s32) = G_ASSERT_SEXT %class:gpr32, 16, implicit-def $w0
%implicit_physreg:gpr(s32) = G_ASSERT_SEXT %class, 16, implicit-def $w0
+...
diff --git a/llvm/test/MachineVerifier/test_g_assert_zext.mir b/llvm/test/MachineVerifier/test_g_assert_zext.mir
index e8dd6910f32a5..ca66feab22890 100644
--- a/llvm/test/MachineVerifier/test_g_assert_zext.mir
+++ b/llvm/test/MachineVerifier/test_g_assert_zext.mir
@@ -1,7 +1,8 @@
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
-# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-name: test
+---
+name: test
body: |
bb.0:
liveins: $x0, $w0
@@ -9,34 +10,35 @@ body: |
%1:_(<4 x s16>) = COPY $x0
%2:_(s32) = COPY $w0
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT expects an immediate operand #2 ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT expects an immediate operand #2
; CHECK: instruction: %assert_zext_1:_(s64) = G_ASSERT_ZEXT
%assert_zext_1:_(s64) = G_ASSERT_ZEXT %0, %0
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT expects an immediate operand #2 ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT expects an immediate operand #2
; CHECK: instruction: %assert_zext_2:_(s64) = G_ASSERT_ZEXT
%assert_zext_2:_(s64) = G_ASSERT_ZEXT %0, i8 8
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
%assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT %0, 8
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT
%assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT %1, 8
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT size must be >= 1 ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT size must be >= 1
; CHECK: instruction: %assert_zext_5:_(s64) = G_ASSERT_ZEXT
%assert_zext_5:_(s64) = G_ASSERT_ZEXT %0, 0
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT size must be less than source bit width ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT size must be less than source bit width
; CHECK: instruction: %assert_zext_6:_(s64) = G_ASSERT_ZEXT
%assert_zext_6:_(s64) = G_ASSERT_ZEXT %0, 128
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %assert_zext_7:_(s64) = G_ASSERT_ZEXT %2:_, 8
%assert_zext_7:_(s64) = G_ASSERT_ZEXT %2, 8
- ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
+ ; CHECK: Bad machine code: Generic instruction cannot have physical register
; CHECK: instruction: %assert_zext_8:_(s64) = G_ASSERT_ZEXT $x0, 8
%assert_zext_8:_(s64) = G_ASSERT_ZEXT $x0, 8
+...
diff --git a/llvm/test/MachineVerifier/test_g_assert_zext_register_bank_class.mir b/llvm/test/MachineVerifier/test_g_assert_zext_register_bank_class.mir
index 8c6448e39f5b6..420ec75c2cadb 100644
--- a/llvm/test/MachineVerifier/test_g_assert_zext_register_bank_class.mir
+++ b/llvm/test/MachineVerifier/test_g_assert_zext_register_bank_class.mir
@@ -1,8 +1,8 @@
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
-# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-name: test
-legalized: true
+---
+name: test
regBankSelected: false
body: |
bb.0:
@@ -10,32 +10,33 @@ body: |
%bank:gpr(s32) = COPY $w0
%class:gpr32(s32) = COPY $w1
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT cannot change register bank
; CHECK: instruction: %bank_mismatch:fpr(s32) = G_ASSERT_ZEXT %bank:gpr, 16
%bank_mismatch:fpr(s32) = G_ASSERT_ZEXT %bank, 16
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT source and destination register classes must match ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT source and destination register classes must match
; CHECK: instruction: %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_ZEXT %class:gpr32, 16
%class_mismatch_gpr:gpr32all(s32) = G_ASSERT_ZEXT %class, 16
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT cannot change register bank
; CHECK: instruction: %class_mismatch_fpr:fpr32(s32) = G_ASSERT_ZEXT %class:gpr32, 16
%class_mismatch_fpr:fpr32(s32) = G_ASSERT_ZEXT %class, 16
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT source and destination register classes must match ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT source and destination register classes must match
; CHECK: instruction: %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_ZEXT %bank:gpr, 16
%dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_ZEXT %bank, 16
- ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
+ ; CHECK: Bad machine code: Generic instruction cannot have physical register
; CHECK: instruction: %implicit_physreg:gpr(s32) = G_ASSERT_ZEXT %class:gpr32, 16, implicit-def $w0
%implicit_physreg:gpr(s32) = G_ASSERT_ZEXT %class, 16, implicit-def $w0
%nothing:_(s32) = G_IMPLICIT_DEF
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT cannot change register bank
; CHECK: %only_dst_has_bank:gpr(s32) = G_ASSERT_ZEXT %nothing:_, 4
%only_dst_has_bank:gpr(s32) = G_ASSERT_ZEXT %nothing, 4
- ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
+ ; CHECK: Bad machine code: G_ASSERT_ZEXT cannot change register bank
; CHECK: %only_dst_has_class:gpr32all(s32) = G_ASSERT_ZEXT %nothing:_, 4
%only_dst_has_class:gpr32all(s32) = G_ASSERT_ZEXT %nothing, 4
+...
diff --git a/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir b/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
index 68593caafc797..61295f17b510c 100644
--- a/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
+++ b/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -mtriple=riscv32 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: riscv-registered-target
# This test checks that the G_BRINDIRECT is an indirect branch by leveraging
@@ -6,15 +6,12 @@
# branch, this test would crash.
---
-name: test_indirect_branch
-legalized: true
-tracksRegLiveness: true
-body: |
+name: test_indirect_branch
+body: |
bb.0:
liveins: $x0
%0:_(p0) = COPY $x0
; CHECK-NOT: Branch instruction is missing a basic block operand or isIndirectBranch property
G_BRINDIRECT %0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_brjt.mir b/llvm/test/MachineVerifier/test_g_brjt.mir
index 1295608cc3d0a..672bedd5ce7df 100644
--- a/llvm/test/MachineVerifier/test_g_brjt.mir
+++ b/llvm/test/MachineVerifier/test_g_brjt.mir
@@ -1,16 +1,16 @@
-# RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_jump_table
-legalized: true
+name: test_jump_table
+legalized: true
tracksRegLiveness: true
jumpTable:
- kind: block-address
+ kind: block-address
entries:
- - id: 0
- blocks: [ '%bb.0' ]
-body: |
+ - id: 0
+ blocks: [ '%bb.0' ]
+body: |
bb.0:
liveins: $x0
%0:_(s64) = COPY $x0
@@ -26,5 +26,4 @@ body: |
; CHECK: G_BRJT src operand 2 must be a scalar reg type
G_BRJT %1, %jump-table.0, %1
-
...
diff --git a/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir b/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
index e5c4d41e1412b..3f6313d95b7a0 100644
--- a/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
+++ b/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -mtriple=riscv32 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: riscv-registered-target
# This test checks that the G_BRJT is an indirect branch by leveraging RISCV's
@@ -6,15 +6,13 @@
# test would crash.
---
-name: test_jump_table
-legalized: true
-tracksRegLiveness: true
+name: test_jump_table
jumpTable:
- kind: block-address
+ kind: block-address
entries:
- - id: 0
- blocks: [ '%bb.0' ]
-body: |
+ - id: 0
+ blocks: [ '%bb.0' ]
+body: |
bb.0:
liveins: $x0
%0:_(s32) = COPY $x0
@@ -22,5 +20,4 @@ body: |
; CHECK-NOT: Branch instruction is missing a basic block operand or isIndirectBranch property
G_BRJT %1, %jump-table.0, %0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_bswap.mir b/llvm/test/MachineVerifier/test_g_bswap.mir
index 679114f06a00e..b6fedd3c69481 100644
--- a/llvm/test/MachineVerifier/test_g_bswap.mir
+++ b/llvm/test/MachineVerifier/test_g_bswap.mir
@@ -1,19 +1,13 @@
-#RUN: not --crash llc -mtriple=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_bswap
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_bswap
+body: |
bb.0:
%0:_(s17) = G_CONSTANT i32 17
; CHECK: Bad machine code: G_BSWAP size must be a multiple of 16 bits
%1:_(s17) = G_BSWAP %0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_build_vector.mir b/llvm/test/MachineVerifier/test_g_build_vector.mir
index 9857306737108..1d91c7d5074fc 100644
--- a/llvm/test/MachineVerifier/test_g_build_vector.mir
+++ b/llvm/test/MachineVerifier/test_g_build_vector.mir
@@ -1,10 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: g_build_vector
-tracksRegLiveness: true
-liveins:
-body: |
+name: g_build_vector
+body: |
bb.0:
%0:_(s32) = IMPLICIT_DEF
diff --git a/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir b/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir
index 296713fce9fe5..fa55af46dbe2e 100644
--- a/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir
+++ b/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir
@@ -1,5 +1,6 @@
-#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown"
@@ -10,15 +11,10 @@
...
---
-name: g_build_vector_trunc
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
+name: g_build_vector_trunc
registers:
- { id: 0, class: _, preferred-register: '' }
-liveins:
-body: |
+body: |
bb.0:
; CHECK: Bad machine code: G_BUILD_VECTOR_TRUNC source operand types are not larger than dest elt type
diff --git a/llvm/test/MachineVerifier/test_g_bzero.mir b/llvm/test/MachineVerifier/test_g_bzero.mir
index 8d88143329802..52af7daf48a0f 100644
--- a/llvm/test/MachineVerifier/test_g_bzero.mir
+++ b/llvm/test/MachineVerifier/test_g_bzero.mir
@@ -1,35 +1,31 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: test_bzero
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_bzero
+body: |
bb.0:
%ptr:_(p0) = G_IMPLICIT_DEF
%cst1:_(s64) = G_CONSTANT i64 4
%cst2:_(s8) = G_CONSTANT i8 7
- ; CHECK: *** Bad machine code: bzero must have 1 memory operand ***
+ ; CHECK: Bad machine code: bzero must have 1 memory operand
G_BZERO %ptr, %cst2, 0
- ; CHECK: *** Bad machine code: bzero memory operand must be a store ***
+ ; CHECK: Bad machine code: bzero memory operand must be a store
G_BZERO %ptr, %cst2, 0 :: (load (s32))
- ; CHECK: *** Bad machine code: Missing mayLoad flag ***
- ; CHECK: *** Bad machine code: bzero memory operand must be a store ***
+ ; CHECK: Bad machine code: Missing mayLoad flag
+ ; CHECK: Bad machine code: bzero memory operand must be a store
G_BZERO %ptr, %cst2, 0 :: (load store (s32))
- ; CHECK: *** Bad machine code: inconsistent bzero address space ***
+ ; CHECK: Bad machine code: inconsistent bzero address space
G_BZERO %ptr, %cst2, 0 :: (store (s32), addrspace 1)
- ; CHECK: *** Bad machine code: bzero operand must be a pointer ***
+ ; CHECK: Bad machine code: bzero operand must be a pointer
G_BZERO %cst1, %cst2, 0 :: (store (s32))
- ; CHECK: *** Bad machine code: 'tail' flag (last operand) must be an immediate 0 or 1 ***
+ ; CHECK: Bad machine code: 'tail' flag (last operand) must be an immediate 0 or 1
G_BZERO %ptr, %cst2, 2 :: (store (s32))
...
diff --git a/llvm/test/MachineVerifier/test_g_concat_vectors.mir b/llvm/test/MachineVerifier/test_g_concat_vectors.mir
index 5c4de1bbc6de7..fd4fceac7db02 100644
--- a/llvm/test/MachineVerifier/test_g_concat_vectors.mir
+++ b/llvm/test/MachineVerifier/test_g_concat_vectors.mir
@@ -1,13 +1,9 @@
-#RUN: not --crash llc -o - -global-isel -mtriple=aarch64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: g_concat_vectors
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: g_concat_vectors
+body: |
bb.0:
%0:_(<2 x s32>) = IMPLICIT_DEF
@@ -19,7 +15,6 @@ body: |
; CHECK: Bad machine code: G_CONCAT_VECTOR requires at least 2 source operands
%3:_(<2 x s32>) = G_CONCAT_VECTORS %1
- ; CHECK: *** Bad machine code: Explicit definition marked as use ***
+ ; CHECK: Bad machine code: Explicit definition marked as use
G_CONCAT_VECTORS %1, %1
-
...
diff --git a/llvm/test/MachineVerifier/test_g_constant.mir b/llvm/test/MachineVerifier/test_g_constant.mir
index 1886c5e11dcd6..d56b8a500956a 100644
--- a/llvm/test/MachineVerifier/test_g_constant.mir
+++ b/llvm/test/MachineVerifier/test_g_constant.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_constant
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_constant
+body: |
bb.0:
; CHECK: Bad machine code: Instruction cannot use a vector result type
; CHECK: Bad machine code: inconsistent constant size
@@ -38,5 +33,4 @@ body: |
; CHECK: Bad machine code: inconsistent constant size
%6:_(p0) = G_CONSTANT i128 0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_constant_pool.mir b/llvm/test/MachineVerifier/test_g_constant_pool.mir
index 828a63554fab3..deb36ac5fcd76 100644
--- a/llvm/test/MachineVerifier/test_g_constant_pool.mir
+++ b/llvm/test/MachineVerifier/test_g_constant_pool.mir
@@ -1,20 +1,14 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_constant_pool
+name: test_constant_pool
constants:
- - id: 0
- value: 'double 3.250000e+00'
+ - id: 0
+ value: 'double 3.250000e+00'
stack:
- { id: 0, size: 64, alignment: 8 }
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+body: |
bb.0:
; CHECK: Bad machine code: Too few operands
diff --git a/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir b/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir
index a280873b826da..782c37f087079 100644
--- a/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir
+++ b/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir
@@ -1,11 +1,9 @@
-# RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_dyn_stackalloc
-legalized: true
-tracksRegLiveness: true
-body: |
+name: test_dyn_stackalloc
+body: |
bb.0:
liveins: $x0
%0:_(s64) = COPY $x0
diff --git a/llvm/test/MachineVerifier/test_g_extract.mir b/llvm/test/MachineVerifier/test_g_extract.mir
index ac5da88e4b4bb..9afce27945d76 100644
--- a/llvm/test/MachineVerifier/test_g_extract.mir
+++ b/llvm/test/MachineVerifier/test_g_extract.mir
@@ -1,14 +1,9 @@
-# RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_extract
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_extract
+body: |
bb.0:
; CHECK: Bad machine code: Too few operands
@@ -31,5 +26,4 @@ body: |
; CHECK: Bad machine code: extract reads past end of register
%8:_(s1) = G_EXTRACT %6, 32
-
...
diff --git a/llvm/test/MachineVerifier/test_g_extract_subvector.mir b/llvm/test/MachineVerifier/test_g_extract_subvector.mir
index 3b9c8314f7cec..b295a31b872ef 100644
--- a/llvm/test/MachineVerifier/test_g_extract_subvector.mir
+++ b/llvm/test/MachineVerifier/test_g_extract_subvector.mir
@@ -1,10 +1,9 @@
-# RUN: not --crash llc -o - -run-pass=none -verify-machineinstrs -mtriple=arm64 %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: g_extract_subvector
-tracksRegLiveness: true
-liveins:
-body: |
+name: g_extract_subvector
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
%1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
@@ -59,5 +58,4 @@ body: |
; CHECK: Index must be a multiple of the destination vector's minimum vector length
%20:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR %12, 1
-
...
diff --git a/llvm/test/MachineVerifier/test_g_fcmp.mir b/llvm/test/MachineVerifier/test_g_fcmp.mir
index 17be746a63ff4..8d137a287d1bb 100644
--- a/llvm/test/MachineVerifier/test_g_fcmp.mir
+++ b/llvm/test/MachineVerifier/test_g_fcmp.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_fcmp
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_fcmp
+body: |
bb.0:
%0:_(s32) = G_FCONSTANT float 0.0
@@ -37,9 +32,8 @@ body: |
%11:_(<vscale x 4 x s1>) = G_FCMP floatpred(oeq), %9, %10
; mismatched scalar element type
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
%12:_(s32) = G_FCONSTANT float 0.0
%13:_(s64) = G_FCONSTANT float 1.0
%14:_(s1) = G_FCMP floatpred(oeq), %12, %13
-
...
diff --git a/llvm/test/MachineVerifier/test_g_fconstant.mir b/llvm/test/MachineVerifier/test_g_fconstant.mir
index d238889f72747..090a7bb1e5b75 100644
--- a/llvm/test/MachineVerifier/test_g_fconstant.mir
+++ b/llvm/test/MachineVerifier/test_g_fconstant.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_fconstant
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_fconstant
+body: |
bb.0:
; CHECK: Bad machine code: Instruction cannot use a vector result type
%0:_(<2 x s32>) = G_FCONSTANT float 0.0
@@ -31,5 +26,4 @@ body: |
; Size is smaller than result
; CHECK: Bad machine code: inconsistent constant size
%4:_(s32) = G_FCONSTANT half 1.0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_icmp.mir b/llvm/test/MachineVerifier/test_g_icmp.mir
index 74e3d34ebb576..b90ebbbd3c917 100644
--- a/llvm/test/MachineVerifier/test_g_icmp.mir
+++ b/llvm/test/MachineVerifier/test_g_icmp.mir
@@ -1,21 +1,16 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_icmp
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_icmp
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CONSTANT i32 1
- ; Vector result, scalar source
- ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
+ ; Vector result, scalar source
+ ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
%2:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1
; Scalar result, vector source
@@ -37,9 +32,8 @@ body: |
%11:_(<vscale x 4 x s1>) = G_ICMP intpred(eq), %9, %10
; mismatched scalar element type
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
%12:_(s32) = G_CONSTANT i32 0
%13:_(s64) = G_CONSTANT i32 1
%14:_(s1) = G_ICMP intpred(eq), %12, %13
-
...
diff --git a/llvm/test/MachineVerifier/test_g_insert.mir b/llvm/test/MachineVerifier/test_g_insert.mir
index cb5834d45c88d..4eee7508f4866 100644
--- a/llvm/test/MachineVerifier/test_g_insert.mir
+++ b/llvm/test/MachineVerifier/test_g_insert.mir
@@ -1,12 +1,9 @@
-# RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_insert
-legalized: true
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_insert
+body: |
bb.0:
; CHECK: Bad machine code: Too few operands
@@ -40,5 +37,4 @@ body: |
; CHECK: Bad machine code: inserted size must be smaller than total register
%9:_(s32) = G_INSERT %3, %3, 0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_insert_subvector.mir b/llvm/test/MachineVerifier/test_g_insert_subvector.mir
index 84cb249d74eb7..33b0a3304b72c 100644
--- a/llvm/test/MachineVerifier/test_g_insert_subvector.mir
+++ b/llvm/test/MachineVerifier/test_g_insert_subvector.mir
@@ -1,11 +1,9 @@
-# RUN: not --crash llc -o - -run-pass=none -verify-machineinstrs -mtriple=arm64 %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: g_splat_vector
-tracksRegLiveness: true
-liveins:
-body: |
+name: g_splat_vector
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
%1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
diff --git a/llvm/test/MachineVerifier/test_g_inttoptr.mir b/llvm/test/MachineVerifier/test_g_inttoptr.mir
index 98e94ddbf6c7d..31bdcdf5cec86 100644
--- a/llvm/test/MachineVerifier/test_g_inttoptr.mir
+++ b/llvm/test/MachineVerifier/test_g_inttoptr.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_inttoptr
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_inttoptr
+body: |
bb.0:
%0:_(s64) = G_IMPLICIT_DEF
@@ -41,5 +36,4 @@ body: |
; CHECK: Bad machine code: operand types must preserve number of vector elements
%10:_(<4 x s64>) = G_IMPLICIT_DEF
%11:_(<2 x p0>) = G_INTTOPTR %10
-
...
diff --git a/llvm/test/MachineVerifier/test_g_invoke_region_start.mir b/llvm/test/MachineVerifier/test_g_invoke_region_start.mir
index 5e6fe2fa7a033..9ecdfc46e7894 100644
--- a/llvm/test/MachineVerifier/test_g_invoke_region_start.mir
+++ b/llvm/test/MachineVerifier/test_g_invoke_region_start.mir
@@ -1,14 +1,9 @@
-#RUN: llc -mtriple=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=aarch64 -global-isel -run-pass=none -o - %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_invoke_start
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_invoke_start
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
@@ -18,5 +13,4 @@ body: |
G_INVOKE_REGION_START
%1:_(s32) = G_ADD %0, %0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_is_fpclass.mir b/llvm/test/MachineVerifier/test_g_is_fpclass.mir
index 0da040cf444b1..8b2c5592e4c9c 100644
--- a/llvm/test/MachineVerifier/test_g_is_fpclass.mir
+++ b/llvm/test/MachineVerifier/test_g_is_fpclass.mir
@@ -33,5 +33,4 @@ body: |
%var7:_(<2 x s1>) = G_IS_FPCLASS %vector:_(<4 x s32>), 1
; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
-
...
diff --git a/llvm/test/MachineVerifier/test_g_jump_table.mir b/llvm/test/MachineVerifier/test_g_jump_table.mir
index b25b0f8b242d6..44d83063304e4 100644
--- a/llvm/test/MachineVerifier/test_g_jump_table.mir
+++ b/llvm/test/MachineVerifier/test_g_jump_table.mir
@@ -1,17 +1,14 @@
-# RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_jump_table
-legalized: true
-tracksRegLiveness: true
+name: test_jump_table
jumpTable:
- kind: block-address
+ kind: block-address
entries:
- - id: 0
- blocks: [ '%bb.0' ]
-liveins:
-body: |
+ - id: 0
+ blocks: [ '%bb.0' ]
+body: |
bb.0:
; CHECK: Bad machine code: Too few operands
@@ -22,5 +19,4 @@ body: |
; CHECK: G_JUMP_TABLE dest operand must have a pointer type
%3:_(s32) = G_JUMP_TABLE %jump-table.0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_llround.mir b/llvm/test/MachineVerifier/test_g_llround.mir
index e69499b1150c1..84e3c8bf07a4d 100644
--- a/llvm/test/MachineVerifier/test_g_llround.mir
+++ b/llvm/test/MachineVerifier/test_g_llround.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -mtriple=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_llround
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_llround
+body: |
bb.0:
liveins: $x0, $q0
%ptr:_(p0) = COPY $x0
@@ -25,3 +20,4 @@ body: |
; CHECK: Bad machine code: operand types must preserve number of vector elements
; CHECK: instruction: %inv_vectors:_(<3 x s32>) = G_LLROUND %vector:_(<2 x s64>)
%inv_vectors:_(<3 x s32>) = G_LLROUND %vector:_(<2 x s64>)
+...
diff --git a/llvm/test/MachineVerifier/test_g_load.mir b/llvm/test/MachineVerifier/test_g_load.mir
index 07c3c0a6b5a24..1d16861d60e1e 100644
--- a/llvm/test/MachineVerifier/test_g_load.mir
+++ b/llvm/test/MachineVerifier/test_g_load.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_load
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_load
+body: |
bb.0:
; CHECK: Bad machine code: Generic memory instruction must access a pointer
@@ -25,5 +20,4 @@ body: |
; CHECK: Bad machine code: atomic load cannot use release ordering
%5:_(s32) = G_LOAD %2 :: (load acq_rel (s32))
-
...
diff --git a/llvm/test/MachineVerifier/test_g_lround.mir b/llvm/test/MachineVerifier/test_g_lround.mir
index 56f06f00049e7..753346e7bede6 100644
--- a/llvm/test/MachineVerifier/test_g_lround.mir
+++ b/llvm/test/MachineVerifier/test_g_lround.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -mtriple=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_lround
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_lround
+body: |
bb.0:
liveins: $x0, $q0
%ptr:_(p0) = COPY $x0
@@ -25,3 +20,4 @@ body: |
; CHECK: Bad machine code: operand types must preserve number of vector elements
; CHECK: instruction: %inv_vectors:_(<3 x s32>) = G_LROUND %vector:_(<2 x s64>)
%inv_vectors:_(<3 x s32>) = G_LROUND %vector:_(<2 x s64>)
+...
diff --git a/llvm/test/MachineVerifier/test_g_memcpy.mir b/llvm/test/MachineVerifier/test_g_memcpy.mir
index d9d728209375b..d2521c2151f95 100644
--- a/llvm/test/MachineVerifier/test_g_memcpy.mir
+++ b/llvm/test/MachineVerifier/test_g_memcpy.mir
@@ -1,13 +1,9 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: test_memcpy
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_memcpy
+body: |
bb.0:
%0:_(p0) = G_CONSTANT i64 0
diff --git a/llvm/test/MachineVerifier/test_g_memcpy_inline.mir b/llvm/test/MachineVerifier/test_g_memcpy_inline.mir
index d49c43b1212e1..501600a556fb6 100644
--- a/llvm/test/MachineVerifier/test_g_memcpy_inline.mir
+++ b/llvm/test/MachineVerifier/test_g_memcpy_inline.mir
@@ -1,13 +1,9 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: test_memcpy_inline
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_memcpy_inline
+body: |
bb.0:
%0:_(p0) = G_CONSTANT i64 0
diff --git a/llvm/test/MachineVerifier/test_g_memmove.mir b/llvm/test/MachineVerifier/test_g_memmove.mir
index d86b34c251e63..fe7f433434bd4 100644
--- a/llvm/test/MachineVerifier/test_g_memmove.mir
+++ b/llvm/test/MachineVerifier/test_g_memmove.mir
@@ -1,55 +1,51 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: test_memmove
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_memmove
+body: |
bb.0:
%0:_(p0) = G_CONSTANT i64 0
%1:_(p0) = G_CONSTANT i64 4
%2:_(s64) = G_CONSTANT i64 4
- ; CHECK: *** Bad machine code: memcpy/memmove must have 2 memory operands ***
+ ; CHECK: Bad machine code: memcpy/memmove must have 2 memory operands
G_MEMMOVE %0, %1, %2, 0
- ; CHECK: *** Bad machine code: memcpy/memmove must have 2 memory operands ***
+ ; CHECK: Bad machine code: memcpy/memmove must have 2 memory operands
G_MEMMOVE %0, %1, %2, 0 :: (load 4)
- ; CHECK: *** Bad machine code: memcpy/memmove must have 2 memory operands ***
+ ; CHECK: Bad machine code: memcpy/memmove must have 2 memory operands
G_MEMMOVE %0, %1, %2, 0 :: (store 4)
- ; CHECK: *** Bad machine code: wrong memory operand types ***
+ ; CHECK: Bad machine code: wrong memory operand types
G_MEMMOVE %0, %1, %2, 0 :: (load 4), (store 4)
- ; CHECK: *** Bad machine code: inconsistent memory operand sizes ***
+ ; CHECK: Bad machine code: inconsistent memory operand sizes
G_MEMMOVE %0, %1, %2, 0 :: (store 8), (load 4)
- ; CHECK: *** Bad machine code: inconsistent memory operand sizes ***
+ ; CHECK: Bad machine code: inconsistent memory operand sizes
G_MEMMOVE %0, %1, %2, 0 :: (store unknown-size), (load 4)
- ; CHECK: *** Bad machine code: inconsistent memory operand sizes ***
+ ; CHECK: Bad machine code: inconsistent memory operand sizes
G_MEMMOVE %0, %1, %2, 0 :: (store 8), (load unknown-size)
- ; CHECK: *** Bad machine code: inconsistent store address space ***
+ ; CHECK: Bad machine code: inconsistent store address space
G_MEMMOVE %0, %1, %2, 0 :: (store 4, addrspace 1), (load 4)
- ; CHECK: *** Bad machine code: inconsistent load address space ***
+ ; CHECK: Bad machine code: inconsistent load address space
G_MEMMOVE %0, %1, %2, 0 :: (store 4), (load 4, addrspace 1)
- ; CHECK: *** Bad machine code: memory instruction operand must be a pointer ***
+ ; CHECK: Bad machine code: memory instruction operand must be a pointer
G_MEMMOVE %2, %0, %2, 0 :: (store 4), (load 4)
- ; CHECK: *** Bad machine code: memory instruction operand must be a pointer ***
+ ; CHECK: Bad machine code: memory instruction operand must be a pointer
G_MEMMOVE %0, %2, %2, 0 :: (store 4), (load 4)
- ; CHECK: *** Bad machine code: 'tail' flag (operand 3) must be an immediate 0 or 1 ***
+ ; CHECK: Bad machine code: 'tail' flag (operand 3) must be an immediate 0 or 1
G_MEMMOVE %0, %0, %2, %0 :: (store 4), (load 4)
- ; CHECK: *** Bad machine code: 'tail' flag (operand 3) must be an immediate 0 or 1 ***
+ ; CHECK: Bad machine code: 'tail' flag (operand 3) must be an immediate 0 or 1
G_MEMMOVE %0, %0, %2, 2 :: (store 4), (load 4)
...
diff --git a/llvm/test/MachineVerifier/test_g_memset.mir b/llvm/test/MachineVerifier/test_g_memset.mir
index ee25b8d6268b7..ec02c8a7a664a 100644
--- a/llvm/test/MachineVerifier/test_g_memset.mir
+++ b/llvm/test/MachineVerifier/test_g_memset.mir
@@ -1,33 +1,28 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: test_memset
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_memset
+body: |
bb.0:
%0:_(p0) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 4
%2:_(s8) = G_CONSTANT i8 7
- ; CHECK: *** Bad machine code: memset must have 1 memory operand ***
+ ; CHECK: Bad machine code: memset must have 1 memory operand
G_MEMSET %0, %1, %2, 0
- ; CHECK: *** Bad machine code: memset memory operand must be a store ***
+ ; CHECK: Bad machine code: memset memory operand must be a store
G_MEMSET %0, %1, %2, 0 :: (load (s32))
- ; CHECK: *** Bad machine code: Missing mayLoad flag ***
- ; CHECK: *** Bad machine code: memset memory operand must be a store ***
+ ; CHECK: Bad machine code: Missing mayLoad flag
+ ; CHECK: Bad machine code: memset memory operand must be a store
G_MEMSET %0, %1, %2, 0 :: (load store (s32))
- ; CHECK: *** Bad machine code: inconsistent memset address space ***
+ ; CHECK: Bad machine code: inconsistent memset address space
G_MEMSET %0, %1, %2, 0 :: (store (s32), addrspace 1)
- ; CHECK: *** Bad machine code: memset operand must be a pointer ***
+ ; CHECK: Bad machine code: memset operand must be a pointer
G_MEMSET %1, %1, %2, 0 :: (store (s32))
-
...
diff --git a/llvm/test/MachineVerifier/test_g_merge_values.mir b/llvm/test/MachineVerifier/test_g_merge_values.mir
index 6713fed857efe..0f73088036135 100644
--- a/llvm/test/MachineVerifier/test_g_merge_values.mir
+++ b/llvm/test/MachineVerifier/test_g_merge_values.mir
@@ -1,10 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: g_merge_values
-tracksRegLiveness: true
-liveins:
-body: |
+name: g_merge_values
+body: |
bb.0:
%0:_(s32) = IMPLICIT_DEF
%1:_(s32) = IMPLICIT_DEF
@@ -24,5 +23,4 @@ body: |
; CHECK: Bad machine code: G_MERGE_VALUES source types do not match
%8:_(s64) = G_MERGE_VALUES %0, %7
-
...
diff --git a/llvm/test/MachineVerifier/test_g_phi.mir b/llvm/test/MachineVerifier/test_g_phi.mir
index 6a1443cacac32..fe6fd2125111b 100644
--- a/llvm/test/MachineVerifier/test_g_phi.mir
+++ b/llvm/test/MachineVerifier/test_g_phi.mir
@@ -1,37 +1,33 @@
-#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
--- |
; ModuleID = 'test.ll'
source_filename = "test.ll"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown"
-
+
define i32 @test_phi(i32 %argc) {
entry:
%cmp = icmp ugt i32 %argc, 0
br i1 %cmp, label %case1, label %case2
-
+
case1: ; preds = %entry
%tmp11 = add i32 %argc, 1
br label %return
-
+
case2: ; preds = %entry
%tmp22 = add i32 %argc, 2
br label %return
-
+
return: ; preds = %case2, %case1
%res = phi i32 [ %tmp11, %case1 ], [ %tmp22, %case2 ]
ret i32 %res
}
-
...
---
-name: test_phi
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
+name: test_phi
+registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
@@ -42,14 +38,13 @@ registers:
- { id: 7, class: _, preferred-register: '' }
- { id: 8, class: _, preferred-register: '' }
- { id: 9, class: _, preferred-register: '' }
-liveins:
body: |
bb.1.entry:
successors: %bb.2.case1(0x40000000), %bb.3.case2(0x40000000)
liveins: $w0
; This test makes sure that the Verifier catches G_PHI with mismatching types.
; CHECK: Bad machine code: Generic Instruction G_PHI has operands with incompatible/missing types
-
+
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 0
%3(s32) = G_CONSTANT i32 1
@@ -58,22 +53,21 @@ body: |
%2(s1) = G_TRUNC %8(s32)
G_BRCOND %2(s1), %bb.2.case1
G_BR %bb.3.case2
-
+
bb.2.case1:
successors: %bb.4.return(0x80000000)
-
+
%4(s32) = G_ADD %0, %3
%9(s16) = G_TRUNC %4(s32)
G_BR %bb.4.return
-
+
bb.3.case2:
successors: %bb.4.return(0x80000000)
-
+
%6(s32) = G_ADD %0, %5
-
+
bb.4.return:
%7(s32) = G_PHI %9(s16), %bb.2.case1, %6(s32), %bb.3.case2
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
-
...
diff --git a/llvm/test/MachineVerifier/test_g_prefetch.mir b/llvm/test/MachineVerifier/test_g_prefetch.mir
index a08b0803fc355..64c400ce725e2 100644
--- a/llvm/test/MachineVerifier/test_g_prefetch.mir
+++ b/llvm/test/MachineVerifier/test_g_prefetch.mir
@@ -1,13 +1,8 @@
-# RUN: not --crash llc -o - -mtriple=aarch64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
name: test_fcmp
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
body: |
bb.0:
liveins: $x0, $w0, $q0
@@ -15,26 +10,26 @@ body: |
%ptr:_(p0) = COPY $x0
G_PREFETCH %ptr
- ; CHECK: *** Bad machine code: Too few operands ***
+ ; CHECK: Bad machine code: Too few operands
; CHECK: 4 operands expected, but 1 given.
G_PREFETCH %ptr, 0, 0, 0, 0
- ; CHECK: *** Bad machine code: Extra explicit operand on non-variadic instruction ***
+ ; CHECK: Bad machine code: Extra explicit operand on non-variadic instruction
; CHECK: operand 4:
G_PREFETCH %s32, 0, 0, 0
- ; CHECK: *** Bad machine code: addr operand must be a pointer ***
+ ; CHECK: Bad machine code: addr operand must be a pointer
; CHECK: operand 0:
G_PREFETCH %ptr, 10, 0, 0
- ; CHECK: *** Bad machine code: rw operand must be an immediate 0-1 ***
+ ; CHECK: Bad machine code: rw operand must be an immediate 0-1
; CHECK: operand 1:
G_PREFETCH %ptr, 0, 10, 0
- ; CHECK: *** Bad machine code: locality operand must be an immediate 0-3 ***
+ ; CHECK: Bad machine code: locality operand must be an immediate 0-3
; CHECK: operand 2:
G_PREFETCH %ptr, 0, 0, 10
- ; CHECK: *** Bad machine code: cache type operand must be an immediate 0-1 ***
+ ; CHECK: Bad machine code: cache type operand must be an immediate 0-1
; CHECK: operand 3:
...
diff --git a/llvm/test/MachineVerifier/test_g_ptr_add.mir b/llvm/test/MachineVerifier/test_g_ptr_add.mir
index 7d1373586c8eb..f01a5f016031c 100644
--- a/llvm/test/MachineVerifier/test_g_ptr_add.mir
+++ b/llvm/test/MachineVerifier/test_g_ptr_add.mir
@@ -1,14 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_gep
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_gep
+body: |
bb.0:
%0:_(p0) = G_IMPLICIT_DEF
diff --git a/llvm/test/MachineVerifier/test_g_ptrmask.mir b/llvm/test/MachineVerifier/test_g_ptrmask.mir
index 5781dac8e033d..c2840c830dbf0 100644
--- a/llvm/test/MachineVerifier/test_g_ptrmask.mir
+++ b/llvm/test/MachineVerifier/test_g_ptrmask.mir
@@ -1,11 +1,9 @@
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
---
-name: test_ptr_mask
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_ptr_mask
+body: |
bb.0:
%0:_(p0) = G_IMPLICIT_DEF
@@ -50,5 +48,4 @@ body: |
; CHECK: Bad machine code: operand types must preserve number of vector elements
%15:_(<4 x p0>) = G_PTRMASK %14, %8
-
...
diff --git a/llvm/test/MachineVerifier/test_g_ptrtoint.mir b/llvm/test/MachineVerifier/test_g_ptrtoint.mir
index b68787f6ef1ae..bfb835f34fba6 100644
--- a/llvm/test/MachineVerifier/test_g_ptrtoint.mir
+++ b/llvm/test/MachineVerifier/test_g_ptrtoint.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_ptrtoint
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_ptrtoint
+body: |
bb.0:
%0:_(s64) = G_IMPLICIT_DEF
@@ -41,5 +36,4 @@ body: |
; CHECK: Bad machine code: operand types must preserve number of vector elements
%10:_(<4 x p0>) = G_IMPLICIT_DEF
%11:_(<2 x s64>) = G_PTRTOINT %10
-
...
diff --git a/llvm/test/MachineVerifier/test_g_rotr_rotl.mir b/llvm/test/MachineVerifier/test_g_rotr_rotl.mir
index ff4c8fb4a14c2..2ef7123032e90 100644
--- a/llvm/test/MachineVerifier/test_g_rotr_rotl.mir
+++ b/llvm/test/MachineVerifier/test_g_rotr_rotl.mir
@@ -1,7 +1,8 @@
-# RUN: not --crash llc -mtriple=arm64 -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: test_uniform
+name: test_uniform
body: |
bb.0:
%src:_(<2 x s64>) = G_IMPLICIT_DEF
@@ -9,5 +10,4 @@ body: |
; CHECK: Shifts and rotates require operands to be either all scalars or all vectors
%rotr:_(<2 x s64>) = G_ROTR %src, %amt
-
...
diff --git a/llvm/test/MachineVerifier/test_g_select.mir b/llvm/test/MachineVerifier/test_g_select.mir
index 5ac8136d74b2a..4630903d0b591 100644
--- a/llvm/test/MachineVerifier/test_g_select.mir
+++ b/llvm/test/MachineVerifier/test_g_select.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -mtriple=aarch64 -run-pass=none -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_select
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_select
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
@@ -27,5 +22,4 @@ body: |
; CHECK: Bad machine code: operand types must preserve number of vector elements
%9:_(<4 x s32>) = G_SELECT %5, %4, %4
-
...
diff --git a/llvm/test/MachineVerifier/test_g_sext_inreg.mir b/llvm/test/MachineVerifier/test_g_sext_inreg.mir
index e675a6f37bbbb..e8047ed57a819 100644
--- a/llvm/test/MachineVerifier/test_g_sext_inreg.mir
+++ b/llvm/test/MachineVerifier/test_g_sext_inreg.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
--- |
@@ -10,7 +10,7 @@
...
---
-name: test
+name: test
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@@ -26,27 +26,27 @@ body: |
%0(s64) = COPY $x0
%1(<4 x s16>) = COPY $x0
- ; CHECK: *** Bad machine code: G_SEXT_INREG expects an immediate operand #2 ***
+ ; CHECK: Bad machine code: G_SEXT_INREG expects an immediate operand #2
; CHECK: instruction: %2:gpr(s64) = G_SEXT_INREG
%2(s64) = G_SEXT_INREG %0, %0
- ; CHECK: *** Bad machine code: G_SEXT_INREG expects an immediate operand #2 ***
+ ; CHECK: Bad machine code: G_SEXT_INREG expects an immediate operand #2
; CHECK: instruction: %3:gpr(s64) = G_SEXT_INREG
%3(s64) = G_SEXT_INREG %0, i8 8
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
%4(<2 x s32>) = G_SEXT_INREG %0, 8
- ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
; CHECK: instruction: %5:gpr(<2 x s32>) = G_SEXT_INREG
%5(<2 x s32>) = G_SEXT_INREG %1, 8
- ; CHECK: *** Bad machine code: G_SEXT_INREG size must be >= 1 ***
+ ; CHECK: Bad machine code: G_SEXT_INREG size must be >= 1
; CHECK: instruction: %6:gpr(s64) = G_SEXT_INREG
%6(s64) = G_SEXT_INREG %0, 0
- ; CHECK: *** Bad machine code: G_SEXT_INREG size must be less than source bit width ***
+ ; CHECK: Bad machine code: G_SEXT_INREG size must be less than source bit width
; CHECK: instruction: %7:gpr(s64) = G_SEXT_INREG
%7(s64) = G_SEXT_INREG %0, 128
...
diff --git a/llvm/test/MachineVerifier/test_g_sextload.mir b/llvm/test/MachineVerifier/test_g_sextload.mir
index 3a39c56245d46..d11a4e9926d51 100644
--- a/llvm/test/MachineVerifier/test_g_sextload.mir
+++ b/llvm/test/MachineVerifier/test_g_sextload.mir
@@ -1,21 +1,16 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_sextload
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_sextload
+body: |
bb.0:
; CHECK: Bad machine code: Generic memory instruction must access a pointer
%0:_(s64) = G_CONSTANT i32 0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s8))
- ; CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+ ; CHECK: Bad machine code: Generic instruction accessing memory must have one mem operand
%2:_(p0) = G_IMPLICIT_DEF
%3:_(s64) = G_SEXTLOAD %2
@@ -24,5 +19,4 @@ body: |
%4:_(s64) = G_SEXTLOAD %2 :: (load (s64))
%5:_(s64) = G_SEXTLOAD %2 :: (load (s128))
-
...
diff --git a/llvm/test/MachineVerifier/test_g_shift.mir b/llvm/test/MachineVerifier/test_g_shift.mir
index 48661314a41f7..1df2c265a7fd2 100644
--- a/llvm/test/MachineVerifier/test_g_shift.mir
+++ b/llvm/test/MachineVerifier/test_g_shift.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=arm64 -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
diff --git a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir
index c4ca2d21cc5f0..7b098ed6a93c2 100644
--- a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir
+++ b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir
@@ -1,10 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: g_shuffle_vector
-tracksRegLiveness: true
-liveins:
-body: |
+name: g_shuffle_vector
+body: |
bb.0:
%0:_(<2 x s32>) = G_IMPLICIT_DEF
%1:_(<2 x s32>) = G_IMPLICIT_DEF
@@ -61,5 +60,4 @@ body: |
; CHECK: Bad machine code: Out of bounds shuffle index
%26:_(<2 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 7)
-
...
diff --git a/llvm/test/MachineVerifier/test_g_splat_vector.mir b/llvm/test/MachineVerifier/test_g_splat_vector.mir
index a5bde496a3f22..0b6abf5d795e9 100644
--- a/llvm/test/MachineVerifier/test_g_splat_vector.mir
+++ b/llvm/test/MachineVerifier/test_g_splat_vector.mir
@@ -1,10 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
---
-name: g_splat_vector
-tracksRegLiveness: true
-liveins:
-body: |
+name: g_splat_vector
+body: |
bb.0:
%0:_(s32) = G_CONSTANT i32 0
%1:_(<2 x s32>) = G_IMPLICIT_DEF
diff --git a/llvm/test/MachineVerifier/test_g_store.mir b/llvm/test/MachineVerifier/test_g_store.mir
index bd9e22b4e2ae5..bd4fd77b301d6 100644
--- a/llvm/test/MachineVerifier/test_g_store.mir
+++ b/llvm/test/MachineVerifier/test_g_store.mir
@@ -1,14 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_store
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_store
+body: |
bb.0:
; CHECK: Bad machine code: Generic memory instruction must access a pointer
@@ -26,5 +21,4 @@ body: |
; CHECK: Bad machine code: atomic store cannot use acquire ordering
G_STORE %1, %2 :: (store acq_rel (s32))
-
...
diff --git a/llvm/test/MachineVerifier/test_g_trunc.mir b/llvm/test/MachineVerifier/test_g_trunc.mir
index f79a748da1788..f28f811370b7f 100644
--- a/llvm/test/MachineVerifier/test_g_trunc.mir
+++ b/llvm/test/MachineVerifier/test_g_trunc.mir
@@ -1,14 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_trunc
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_trunc
+body: |
bb.0:
; CHECK: Bad machine code: Too few operands
@@ -19,5 +14,4 @@ body: |
; CHECK: Bad machine code: Too few operands
; CHECK: Bad machine code: Explicit definition marked as use
G_TRUNC %1
-
...
diff --git a/llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir b/llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir
index 71d2ee0e10c59..4ce40c9bdc7c9 100644
--- a/llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir
+++ b/llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir
@@ -1,15 +1,15 @@
-# RUN: not --crash llc -mtriple=arm64 -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
-name: test
+name: test
body: |
bb.0:
%v1:_(<2 x s64>) = G_IMPLICIT_DEF
%v2:_(<2 x s64>) = G_IMPLICIT_DEF
%v3:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK: *** Bad machine code: Bitfield extraction is not supported on vectors ***
+ ; CHECK: Bad machine code: Bitfield extraction is not supported on vectors
%ubfx_vector:_(<2 x s64>) = G_UBFX %v1, %v2, %v3
- ; CHECK: *** Bad machine code: Bitfield extraction is not supported on vectors ***
+ ; CHECK: Bad machine code: Bitfield extraction is not supported on vectors
%sbfx_vector:_(<2 x s64>) = G_SBFX %v1, %v2, %v3
...
diff --git a/llvm/test/MachineVerifier/test_g_ubsantrap.mir b/llvm/test/MachineVerifier/test_g_ubsantrap.mir
index d2b219d8650ac..ab84b22b89c79 100644
--- a/llvm/test/MachineVerifier/test_g_ubsantrap.mir
+++ b/llvm/test/MachineVerifier/test_g_ubsantrap.mir
@@ -1,11 +1,9 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_ubsantrap
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_ubsantrap
+body: |
bb.0:
; CHECK: Crash kind must be 8 bit wide
@@ -14,5 +12,4 @@ body: |
; CHECK: Crash kind must be an immediate
%5:_(s32) = IMPLICIT_DEF
G_UBSANTRAP %5
-
...
diff --git a/llvm/test/MachineVerifier/test_g_unmerge_values.mir b/llvm/test/MachineVerifier/test_g_unmerge_values.mir
index d16854890f7d8..174f31c02716d 100644
--- a/llvm/test/MachineVerifier/test_g_unmerge_values.mir
+++ b/llvm/test/MachineVerifier/test_g_unmerge_values.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
diff --git a/llvm/test/MachineVerifier/test_g_vscale.mir b/llvm/test/MachineVerifier/test_g_vscale.mir
index f4ff76766a84e..20ee59a02ce86 100644
--- a/llvm/test/MachineVerifier/test_g_vscale.mir
+++ b/llvm/test/MachineVerifier/test_g_vscale.mir
@@ -1,16 +1,15 @@
-# RUN: not --crash llc -verify-machineinstrs -mtriple=arm64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: g_vscale
+name: g_vscale
body: |
bb.0:
+ %1:_(s32) = G_CONSTANT i32 4
- %1:_(s32) = G_CONSTANT i32 4
+ ; CHECK: G_VSCALE operand must be cimm
+ %2:_(s32) = G_VSCALE %1
- ; CHECK: G_VSCALE operand must be cimm
- %2:_(s32) = G_VSCALE %1
-
- ; CHECK: G_VSCALE immediate cannot be zero
- %3:_(s32) = G_VSCALE i32 0
+ ; CHECK: G_VSCALE immediate cannot be zero
+ %3:_(s32) = G_VSCALE i32 0
...
diff --git a/llvm/test/MachineVerifier/test_g_zextload.mir b/llvm/test/MachineVerifier/test_g_zextload.mir
index 1a3ecec158f95..112c22e03ea84 100644
--- a/llvm/test/MachineVerifier/test_g_zextload.mir
+++ b/llvm/test/MachineVerifier/test_g_zextload.mir
@@ -1,21 +1,16 @@
-# RUN: not --crash llc -o - -mtriple=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_zextload
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_zextload
+body: |
bb.0:
; CHECK: Bad machine code: Generic memory instruction must access a pointer
%0:_(s64) = G_CONSTANT i32 0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s8))
- ; CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+ ; CHECK: Bad machine code: Generic instruction accessing memory must have one mem operand
%2:_(p0) = G_IMPLICIT_DEF
%3:_(s64) = G_ZEXTLOAD %2
@@ -24,5 +19,4 @@ body: |
%4:_(s64) = G_ZEXTLOAD %2 :: (load (s64))
%5:_(s64) = G_ZEXTLOAD %2 :: (load (s128))
-
...
diff --git a/llvm/test/MachineVerifier/test_insert_subreg.mir b/llvm/test/MachineVerifier/test_insert_subreg.mir
index a3c98cd7625f7..80eabb598dd56 100644
--- a/llvm/test/MachineVerifier/test_insert_subreg.mir
+++ b/llvm/test/MachineVerifier/test_insert_subreg.mir
@@ -1,14 +1,9 @@
-#RUN: not --crash llc -mtriple=aarch64 -o - -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_insert_subreg
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
+name: test_insert_subreg
+body: |
bb.0:
liveins: $s0, $h1, $q2
@@ -16,21 +11,20 @@ body: |
; FIXME: we can't diagnose this case because the ARM backend treats fp16
; values as being ssub regs, creating a contradiction in the sizes.
- ; CHECK-NOT: *** Bad machine code:
+ ; CHECK-NOT: Bad machine code:
%1:fpr128 = IMPLICIT_DEF
%2:fpr128 = INSERT_SUBREG %1:fpr128, %0:fpr32, %subreg.hsub
- ; CHECK: *** Bad machine code: INSERT_SUBREG expected inserted value to have equal or lesser size than the subreg it was inserted into ***
+ ; CHECK: Bad machine code: INSERT_SUBREG expected inserted value to have equal or lesser size than the subreg it was inserted into
%3:fpr128 = IMPLICIT_DEF
%4:fpr128 = INSERT_SUBREG %3:fpr128, %0:fpr32, %subreg.dsub
- ; CHECK-NOT: *** Bad machine code:
+ ; CHECK-NOT: Bad machine code:
%7:fpr128 = IMPLICIT_DEF
%8:fpr128 = INSERT_SUBREG %7:fpr128, %0:fpr32, %subreg.ssub
- ; CHECK-NOT: *** Bad machine code:
+ ; CHECK-NOT: Bad machine code:
%9:fpr128 = COPY $q2
%10:fpr128 = IMPLICIT_DEF
%11:fpr128 = INSERT_SUBREG %10:fpr128, %9.ssub, %subreg.ssub
-
...
diff --git a/llvm/test/MachineVerifier/test_multiple_errors.mir b/llvm/test/MachineVerifier/test_multiple_errors.mir
index e1ce348565c1a..5a588e5f0238e 100644
--- a/llvm/test/MachineVerifier/test_multiple_errors.mir
+++ b/llvm/test/MachineVerifier/test_multiple_errors.mir
@@ -1,22 +1,20 @@
-# RUN: not --crash llc -mtriple=aarch64 -o /dev/null -run-pass=none %s 2>&1 | FileCheck %s --implicit-check-not="Bad machine code"
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
# Since we abort after reporting the first error, we should only expect one error to be reported.
-# CHECK: *** Bad machine code: Generic virtual register use cannot be undef ***
+# CHECK: Bad machine code: Generic virtual register use cannot be undef
# CHECK: Found 1 machine code errors.
---
-name: foo
-liveins:
-body: |
+name: foo
+body: |
bb.0:
$x0 = COPY undef %0:_(s64)
...
---
-name: bar
-liveins:
-body: |
+name: bar
+body: |
bb.0:
$x0 = COPY undef %0:_(s64)
...
diff --git a/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir b/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir
index 0253e6ab952c6..51656166321c5 100644
--- a/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir
+++ b/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -run-pass=machineverifier %s -o - 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
--- |
@@ -26,7 +26,7 @@
...
---
-name: valid
+name: valid
tracksRegLiveness: true
body: |
bb.0.entry:
@@ -54,7 +54,7 @@ body: |
...
---
-name: broken
+name: broken
tracksRegLiveness: true
body: |
bb.0.entry:
diff --git a/llvm/test/MachineVerifier/test_step-vector.mir b/llvm/test/MachineVerifier/test_step-vector.mir
index b4a01bb258da1..d8d7b2fb5df1d 100644
--- a/llvm/test/MachineVerifier/test_step-vector.mir
+++ b/llvm/test/MachineVerifier/test_step-vector.mir
@@ -1,8 +1,8 @@
-# RUN: not --crash llc -verify-machineinstrs -mtriple=arm64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: g_step_vector
+name: g_step_vector
body: |
bb.0:
@@ -24,6 +24,4 @@ body: |
%6:_(<vscale x 2 x s33>) = G_STEP_VECTOR i32 56
%7:_(<vscale x 2 x s128>) = G_STEP_VECTOR i128 79
-
...
-
diff --git a/llvm/test/MachineVerifier/test_uscmp.mir b/llvm/test/MachineVerifier/test_uscmp.mir
index 4e518749e7377..6187e73e4bc70 100644
--- a/llvm/test/MachineVerifier/test_uscmp.mir
+++ b/llvm/test/MachineVerifier/test_uscmp.mir
@@ -1,9 +1,9 @@
-# RUN: not --crash llc -verify-machineinstrs -run-pass none -mtriple=arm64 -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
-name: test_uscmp
-body: |
+name: test_uscmp
+body: |
bb.0:
%2:_(p0) = G_IMPLICIT_DEF
@@ -30,6 +30,4 @@ body: |
%19:_(s32) = G_CONSTANT i32 2
; CHECK: Result type must be at least 2 bits wide
%20:_(s1) = G_SCMP %18, %19
-
-
...
diff --git a/llvm/test/MachineVerifier/test_vector_reductions.mir b/llvm/test/MachineVerifier/test_vector_reductions.mir
index 6ea611ecab96b..d904ec325d8aa 100644
--- a/llvm/test/MachineVerifier/test_vector_reductions.mir
+++ b/llvm/test/MachineVerifier/test_vector_reductions.mir
@@ -1,5 +1,6 @@
-# RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=aarch64 -global-isel -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
+
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown"
@@ -10,12 +11,8 @@
...
---
-name: vector_reductions
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-body: |
+name: vector_reductions
+body: |
bb.0:
%vec_v2s64:_(<2 x s64>) = IMPLICIT_DEF
@@ -29,5 +26,4 @@ body: |
%dst:_(s64) = G_VECREDUCE_SEQ_FADD %scalar_s64, %scalar_s64
; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction must have a vector 2nd operand
-
...
diff --git a/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir b/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir
index 38cf1859e6d1a..8368c2dfe60fd 100644
--- a/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir
+++ b/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: x86-registered-target
# CHECK: Bad machine code: Generic extend/truncate can not operate on pointers
@@ -21,7 +21,7 @@
# CHECK-NEXT: - basic block: %bb.4
# CHECK-NEXT: - instruction: %ae_i32:_(s32) = G_ANYEXT %i32:_(s32)
-# CHECK: Bad machine code: Generic truncate has destination type no smaller than source ***
+# CHECK: Bad machine code: Generic truncate has destination type no smaller than source
# CHECK-NEXT: - function: bad_generic_extends_and_truncates
# CHECK-NEXT: - basic block: %bb.5
# CHECK-NEXT: - instruction: %ft_f32:_(s64) = G_FPTRUNC %f32:_(s32)
@@ -54,9 +54,8 @@
# CHECK-NEXT: - instruction: %fe_v2f128:_(p0) = G_FPEXT %v2f128:_(<2 x s128>)
---
-name: bad_generic_extends_and_truncates
-tracksRegLiveness: true
-body: |
+name: bad_generic_extends_and_truncates
+body: |
bb.0:
liveins: $rdi, $esi, $rdx, $xmm0, $ymm1, $ymm2
diff --git a/llvm/test/MachineVerifier/verifier-generic-types-1.mir b/llvm/test/MachineVerifier/verifier-generic-types-1.mir
index 884209f173626..eeb3cecfe4472 100644
--- a/llvm/test/MachineVerifier/verifier-generic-types-1.mir
+++ b/llvm/test/MachineVerifier/verifier-generic-types-1.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: x86-registered-target
# CHECK-NOT: Type mismatch
@@ -12,9 +12,8 @@
# CHECK-NOT: Type mismatch
---
-name: first_type_of_a_type_index_missing_and_no_mismatches
-tracksRegLiveness: true
-body: |
+name: first_type_of_a_type_index_missing_and_no_mismatches
+body: |
bb.0:
liveins: $rdi, $rsi
diff --git a/llvm/test/MachineVerifier/verifier-generic-types-2.mir b/llvm/test/MachineVerifier/verifier-generic-types-2.mir
index 5558a2b654ac1..6e9137de19e2d 100644
--- a/llvm/test/MachineVerifier/verifier-generic-types-2.mir
+++ b/llvm/test/MachineVerifier/verifier-generic-types-2.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: x86-registered-target
# CHECK: Bad machine code: Generic instruction is missing a virtual register type
@@ -14,9 +14,8 @@
# CHECK-NEXT: - operand 2: %1:_(s32)
---
-name: first_type_of_a_type_index_missing_and_a_mismatch
-tracksRegLiveness: true
-body: |
+name: first_type_of_a_type_index_missing_and_a_mismatch
+body: |
bb.0:
liveins: $rdi, $esi
diff --git a/llvm/test/MachineVerifier/verifier-phi-fail0.mir b/llvm/test/MachineVerifier/verifier-phi-fail0.mir
index aa488f064cc65..2d446783875e0 100644
--- a/llvm/test/MachineVerifier/verifier-phi-fail0.mir
+++ b/llvm/test/MachineVerifier/verifier-phi-fail0.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: x86-registered-target
---
diff --git a/llvm/test/MachineVerifier/verifier-phi.mir b/llvm/test/MachineVerifier/verifier-phi.mir
index 6eb35b9853441..23d39c6bbb6df 100644
--- a/llvm/test/MachineVerifier/verifier-phi.mir
+++ b/llvm/test/MachineVerifier/verifier-phi.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none | FileCheck %s
+# RUN: llc -o - %s -mtriple=x86_64 -run-pass=none | FileCheck %s
# REQUIRES: x86-registered-target
# This should cleanly pass the machine verifier
diff --git a/llvm/test/MachineVerifier/verifier-statepoint.mir b/llvm/test/MachineVerifier/verifier-statepoint.mir
index c5c1717530dae..e1bb28b6fd1a1 100644
--- a/llvm/test/MachineVerifier/verifier-statepoint.mir
+++ b/llvm/test/MachineVerifier/verifier-statepoint.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: x86-registered-target
# CHECK: Bad machine code: STATEPOINT defs expected to be tied
diff --git a/llvm/test/MachineVerifier/verify-inlineasmbr.mir b/llvm/test/MachineVerifier/verify-inlineasmbr.mir
index aaf3f97fcdee0..7c8226459c440 100644
--- a/llvm/test/MachineVerifier/verify-inlineasmbr.mir
+++ b/llvm/test/MachineVerifier/verify-inlineasmbr.mir
@@ -1,5 +1,4 @@
-# RUN: not --crash llc -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 \
-# RUN: | FileCheck %s
+# RUN: not --crash llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: powerpc-registered-target
# Test for a case we observed after the initial implementation of D129997
@@ -54,7 +53,6 @@
}
attributes #0 = { argmemonly nocallback nofree nosync nounwind willreturn }
-
...
---
name: ceph_con_v2_try_read
@@ -174,5 +172,4 @@ body: |
LIFETIME_END %stack.0.skip.i.i
B %bb.1
-
...
diff --git a/llvm/test/MachineVerifier/verify-regbankselected-dbg-undef-use.mir b/llvm/test/MachineVerifier/verify-regbankselected-dbg-undef-use.mir
index 2745096079631..2b7e99efb2dd3 100644
--- a/llvm/test/MachineVerifier/verify-regbankselected-dbg-undef-use.mir
+++ b/llvm/test/MachineVerifier/verify-regbankselected-dbg-undef-use.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
--- |
diff --git a/llvm/test/MachineVerifier/verify-regbankselected.mir b/llvm/test/MachineVerifier/verify-regbankselected.mir
index ed022ed5eaf9d..b379b3ab4b430 100644
--- a/llvm/test/MachineVerifier/verify-regbankselected.mir
+++ b/llvm/test/MachineVerifier/verify-regbankselected.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
--- |
@@ -9,7 +9,7 @@
...
---
-# CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
+# CHECK: Bad machine code: Generic virtual register must have a bank in a RegBankSelected function
# CHECK: instruction: %0:_(s64) = COPY
# CHECK: operand 0: %0
name: test
diff --git a/llvm/test/MachineVerifier/verify-regops.mir b/llvm/test/MachineVerifier/verify-regops.mir
index f8903954e28f8..0d976e220c444 100644
--- a/llvm/test/MachineVerifier/verify-regops.mir
+++ b/llvm/test/MachineVerifier/verify-regops.mir
@@ -1,5 +1,4 @@
-# RUN: not --crash llc -mtriple=i686 -o - %s -run-pass=none -verify-machineinstrs \
-# RUN: 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=i686 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: x86-registered-target
#
# Check that MachineVerifier catches corrupt operands where MO->isReg()
@@ -9,21 +8,21 @@
# CHECK-LABEL: fun
-# CHECK: *** Bad machine code: Expected a register operand. ***
+# CHECK: Bad machine code: Expected a register operand
# CHECK: - instruction: %1:gr32 = XOR32rm -1, %fixed-stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %fixed-stack.1, align 8)
# CHECK: - operand 1: -1
-# CHECK: *** Bad machine code: Expected a non-register operand. ***
+# CHECK: Bad machine code: Expected a non-register operand
# CHECK: - instruction: %2:gr32 = OR32ri %1:gr32(tied-def 0), %0:gr32, implicit-def dead $eflags
# CHECK: - operand 2: %0:gr32
-name: fun
+name: fun
tracksRegLiveness: true
fixedStack:
- { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
- { id: 3, size: 4, alignment: 16, isImmutable: true }
-body: |
+body: |
bb.0:
%0:gr32 = MOV32rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.3, align 16)
; Was: %1:gr32 = XOR32rm %0, %fixed-stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %fixed-stack.1, align 8)
diff --git a/llvm/test/MachineVerifier/verify-selected-dbg-undef-use.mir b/llvm/test/MachineVerifier/verify-selected-dbg-undef-use.mir
index 1c3e0f22e698c..8228a2ebdc7c6 100644
--- a/llvm/test/MachineVerifier/verify-selected-dbg-undef-use.mir
+++ b/llvm/test/MachineVerifier/verify-selected-dbg-undef-use.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
--- |
diff --git a/llvm/test/MachineVerifier/verify-selected.mir b/llvm/test/MachineVerifier/verify-selected.mir
index b14f977caf148..0237f1508b3e3 100644
--- a/llvm/test/MachineVerifier/verify-selected.mir
+++ b/llvm/test/MachineVerifier/verify-selected.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
--- |
@@ -10,7 +10,7 @@
...
---
-name: test
+name: test
regBankSelected: true
selected: true
registers:
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