[llvm] [missed-opt][isel] Unnecessary shift count masking in 128 bit arithmetic (PR #172506)

[Craig Topper via llvm-commits]

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@@ -10542,6 +10542,21 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
       return DAG.getNode(ISD::SHL, DL, VT, N0, NewOp1);
   }
 
+  // fold (shl x, (and y, 63)) -> (shl x, y)
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topperc wrote:

This transform isn't valid by the semantics of SelectionDAG and LLVM IR. The whole shift amount is used. Not all targets ignore upper bits of the shift amount. For example, i8 and i16 shift instructions on X86 mask the shift amount to 5 bits not 3 or 4 bits.

https://github.com/llvm/llvm-project/pull/172506