[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)

[YunQiang Su via llvm-commits]

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@@ -11919,38 +11928,70 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
                                        const TargetLowering &TLI,
                                        SelectionDAG &DAG) {
   EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+  unsigned IEEE2019NumOpcode = 0;
+  unsigned IEEE2019Opcode = 0;
+  unsigned IEEEOpcode = 0;
+  unsigned Opcode = 0;
   switch (CC) {
   case ISD::SETOLT:
   case ISD::SETOLE:
   case ISD::SETLT:
   case ISD::SETLE:
   case ISD::SETULT:
   case ISD::SETULE: {
-    // Since it's known never nan to get here already, either fminnum or
-    // fminnum_ieee are OK. Try the ieee version first, since it's fminnum is
-    // expanded in terms of it.
-    unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
-    if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
-      return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
-
-    unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
-    if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
-      return DAG.getNode(Opcode, DL, VT, LHS, RHS);
-    return SDValue();
+    // Since it's known never nan to get here already, either fminimumnum,
+    // fminimum, fminnum, or fminnum_ieee are OK. Try Legal first and then
+    // Custom.
+    IEEE2019NumOpcode = LHS == True ? ISD::FMINIMUMNUM : ISD::FMAXIMUMNUM;
+    IEEE2019Opcode = LHS == True ? ISD::FMINIMUM : ISD::FMAXIMUM;
+    IEEEOpcode = LHS == True ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
+    Opcode = LHS == True ? ISD::FMINNUM : ISD::FMAXNUM;
   }
+    [[fallthrough]];
   case ISD::SETOGT:
   case ISD::SETOGE:
   case ISD::SETGT:
   case ISD::SETGE:
   case ISD::SETUGT:
   case ISD::SETUGE: {
-    unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
-    if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
+    if (Opcode == 0) {
+      // Since it's known never nan to get here already, either fminimumnum,
+      // fminimum, fminnum, or fminnum_ieee are OK. Try Legal first and then
+      // Custom.
+      IEEE2019NumOpcode = (LHS == True) ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
+      IEEE2019Opcode = (LHS == True) ? ISD::FMAXIMUM : ISD::FMINIMUM;
+      IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
+      Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
+    }
+    // Try FMINIMUM/FMAXIMUM first as it has smaller codesize on AMDGPU GFX12.
+    if (TLI.isOperationLegal(IEEE2019Opcode, VT))
+      return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
+    if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
+      return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
+    if (TLI.isOperationLegal(IEEEOpcode, VT))
       return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
+    if (TLI.isOperationLegal(Opcode, VT))
+      return DAG.getNode(Opcode, DL, VT, LHS, RHS);
+
+    // X86 has combineFMinFMax
+    if (TLI.hasTargetDAGCombine((ISD::NodeType)IEEE2019Opcode) ||
+        TLI.hasTargetDAGCombine((ISD::NodeType)IEEE2019NumOpcode) ||
+        TLI.hasTargetDAGCombine((ISD::NodeType)IEEEOpcode) ||
+        TLI.hasTargetDAGCombine((ISD::NodeType)Opcode))
+      return SDValue();
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wzssyqa wrote:

Ohh, yes, we can do it by set Flags nnan/nsz for getNode(MinMaxOpc)

https://github.com/llvm/llvm-project/pull/137449