[llvm] [RISCV] Guard zero-stride load SchedPredicate with subtarget feature as well (PR #172111)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 14 19:38:58 PST 2025

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https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/172111

Previous message: [llvm] [RISCV] Custom legalize i32 saddo/ssubo on RV64 to return a sign extended value for the data result. (PR #172112)
Next message: [llvm] [TableGen][SchedModel] Add logical combiners for SchedPredicates (PR #172106)
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