[llvm] [AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (PR #172057)

[Nicolai Hähnle via llvm-commits]

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@@ -6,24 +6,34 @@
 //
 //===----------------------------------------------------------------------===//
 //
-/// \file This file contains a DAG scheduling mutation to add latency to
-///       barrier edges between ATOMIC_FENCE instructions and preceding
-///       memory accesses potentially affected by the fence.
-///       This encourages the scheduling of more instructions before
-///       ATOMIC_FENCE instructions.  ATOMIC_FENCE instructions may
-///       introduce wait counting or indicate an impending S_BARRIER
-///       wait.  Having more instructions in-flight across these
-///       constructs improves latency hiding.
+/// \file This file contains a DAG scheduling mutation to add latency to:
+///       1. Barrier edges between ATOMIC_FENCE instructions and preceding
+///          memory accesses potentially affected by the fence.
+///          This encourages the scheduling of more instructions before
+///          ATOMIC_FENCE instructions.  ATOMIC_FENCE instructions may
+///          introduce wait counting or indicate an impending S_BARRIER
+///          wait.  Having more instructions in-flight across these
+///          constructs improves latency hiding.
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nhaehnle wrote:

This is pre-existing and makes sense, but it raises something that it would be good to follow up on: we get an ATOMIC_FENCE for explicit LLVM IT `fence` instructions, but `atomicrmw` and `cmpxchg` with release ordering have the same waits...

https://github.com/llvm/llvm-project/pull/172057