[llvm] [SDAG] fix miss opt: shl nuw + zext adds unnecessary masking (PR #172046)

[via llvm-commits]

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@@ -1572,6 +1572,9 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
   assert(VT.bitsLE(OpVT) && "Not extending!");
   if (OpVT == VT)
     return Op;
+  if (Op.getOpcode() == ISD::AssertZext &&
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actinks wrote:

Yes, DAGCombiner should handle this automatically. It is indeed working here—the issue appears to stem from the zero_extent (i.e., truncate nuw) optimization not working as expected.

`Legalizing: t17: i16 = truncate nuw t16
Legal node: nothing to do

Combining: t17: i16 = truncate nuw t16

Replacing.2 t15: i32 = and t4, Constant:i32<65535>

With: t4: i32 = AssertZext t2, ValueType:ch:i16


Legalizing: t17: i16 = truncate t16
Legal node: nothing to do

Combining: t17: i16 = truncate t16

Legalizing: t16: i32 = shl t4, Constant:i8<3>
Legal node: nothing to do

Combining: t16: i32 = shl t4, Constant:i8<3>

Legalizing: t9: i32 = zero_extend t17
Legal node: nothing to do

Combining: t9: i32 = zero_extend t17
Creating constant: t18: i32 = Constant<65535>
Creating new node: t19: i32 = and t16, Constant:i32<65535>
 ... into: t19: i32 = and t16, Constant:i32<65535>`

https://github.com/llvm/llvm-project/pull/172046