[llvm] Precommit test for PR #172046 (PR #172127)

[via llvm-commits]

https://github.com/actinks created https://github.com/llvm/llvm-project/pull/172127

None

>From a3c74a07208a85ad7c36b32bdcd11b6ed24b35ab Mon Sep 17 00:00:00 2001
From: actink <actink at 163.com>
Date: Sat, 13 Dec 2025 13:53:18 +0800
Subject: [PATCH] Precommit test for PR #172046

---
 llvm/test/CodeGen/X86/pr172046.ll | 50 +++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/pr172046.ll

diff --git a/llvm/test/CodeGen/X86/pr172046.ll b/llvm/test/CodeGen/X86/pr172046.ll
new file mode 100644
index 0000000000000..bbd23d2339701
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr172046.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
+
+define i32 @_Z1ft(i16 zeroext %0) {
+; X86-LABEL: _Z1ft:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    shll $3, %eax
+; X86-NEXT:    movzwl %ax, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: _Z1ft:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    shll $3, %edi
+; X64-NEXT:    movzwl %di, %eax
+; X64-NEXT:    retq
+entry:
+  %3 = shl nuw i16 %0, 3
+  %4 = zext i16 %3 to i32
+  ret i32 %4
+}
+
+define i32 @_Z1gt(i16 zeroext %x) {
+; X86-LABEL: _Z1gt:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl %eax, %ecx
+; X86-NEXT:    andl $8191, %ecx # imm = 0x1FFF
+; X86-NEXT:    shll $16, %eax
+; X86-NEXT:    leal (%eax,%ecx,8), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: _Z1gt:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8191, %eax # imm = 0x1FFF
+; X64-NEXT:    shll $16, %edi
+; X64-NEXT:    leal (%rdi,%rax,8), %eax
+; X64-NEXT:    retq
+entry:
+  %conv = zext nneg i16 %x to i32
+  %shl = shl nuw i16 %x, 3
+  %conv3 = zext i16 %shl to i32
+  %shl5 = shl nuw nsw i32 %conv, 16
+  %or = or disjoint i32 %shl5, %conv3
+  ret i32 %or
+}
+