[llvm] [SDAG] fix miss opt: shl nuw + zext adds unnecessary masking (PR #172046)

[via llvm-commits]

actinks wrote:

> Have you looked at doing this in SelectionDAGBuilder with the other AssertZExt/AssertSExt handling? Ideally this needs to be attached to the corresponding CopyFromRegs node.

The zeroext flag is indeed generated at the IR level (e.g., i32 @_Z1ft(i16 noundef zeroext %0)), and during SelectionDAGBuilder::LowerArguments, this results in a node like t4: i32 = AssertZext t2, ValueType:ch:i16. However, at this stage, we don’t have enough context to determine the actual number of meaningful bits in the argument (e.g., that it’s effectively zero-extended from i13 rather than i16). Therefore, we can’t accurately emit AssertZext t2, ValueType:ch:i13 during argument lowering. The precise known-zero information (like bits [13, 15] being zero due to shl nuw) only becomes available later.


https://github.com/llvm/llvm-project/pull/172046