[llvm] [AMDGPU] Add support for GFX12 expert scheduling mode 2 (PR #170319)

[Nicolai Hähnle via llvm-commits]

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@@ -356,6 +447,35 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
 ; GFX12-SPREFETCH-NEXT:  .LBB3_2: ; %for.end
 ; GFX12-SPREFETCH-NEXT:    s_endpgm
 ;
+; GFX12ES2-SPREFETCH-LABEL: copy_local:
+; GFX12ES2-SPREFETCH:       ; %bb.0: ; %entry
+; GFX12ES2-SPREFETCH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), 2
+; GFX12ES2-SPREFETCH-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12ES2-SPREFETCH-NEXT:    s_wait_kmcnt 0x0
+; GFX12ES2-SPREFETCH-NEXT:    s_cmp_eq_u32 s2, 0
+; GFX12ES2-SPREFETCH-NEXT:    s_cbranch_scc1 .LBB3_2
+; GFX12ES2-SPREFETCH-NEXT:  .LBB3_1: ; %for.body
+; GFX12ES2-SPREFETCH-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX12ES2-SPREFETCH-NEXT:    s_wait_alu depctr_sa_sdst(0) depctr_vm_vsrc(0)
+; GFX12ES2-SPREFETCH-NEXT:    v_mov_b32_e32 v2, s1
+; GFX12ES2-SPREFETCH-NEXT:    v_mov_b32_e32 v4, s0
+; GFX12ES2-SPREFETCH-NEXT:    s_add_co_i32 s2, s2, -1
+; GFX12ES2-SPREFETCH-NEXT:    s_add_co_i32 s0, s0, 16
+; GFX12ES2-SPREFETCH-NEXT:    s_add_co_i32 s1, s1, 16
+; GFX12ES2-SPREFETCH-NEXT:    s_wait_alu depctr_va_vdst(1)
+; GFX12ES2-SPREFETCH-NEXT:    ds_load_2addr_b32 v[0:1], v2 offset0:2 offset1:3
+; GFX12ES2-SPREFETCH-NEXT:    s_wait_alu depctr_vm_vsrc(0)
+; GFX12ES2-SPREFETCH-NEXT:    ds_load_2addr_b32 v[2:3], v2 offset1:1
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nhaehnle wrote:

This shows a problematic weakness in the code gen quality. The wait for vm_vsrc(0) here hurts. Presumably we insert it because the second ds_load_2addr_b32 writes to v[2:3]. However, that write will necessarily happen after the read of v2 because the instructions fetch their source operands in-order and only write their results after the sources have been fetched.

https://github.com/llvm/llvm-project/pull/170319