[llvm] d901485 - [Mips] Add compact branch patterns for MipsR6 (#171131)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 12 11:55:16 PST 2025
Author: ArielCPU
Date: 2025-12-12T20:55:12+01:00
New Revision: d901485655b978874f22bf50d9d6fc01331fffcb
URL: https://github.com/llvm/llvm-project/commit/d901485655b978874f22bf50d9d6fc01331fffcb
DIFF: https://github.com/llvm/llvm-project/commit/d901485655b978874f22bf50d9d6fc01331fffcb.diff
LOG: [Mips] Add compact branch patterns for MipsR6 (#171131)
Added patterns for combining set and branch into one compact branch
The patterns are disabled if -mips-compact-branches=never
Added:
llvm/test/CodeGen/Mips/compact-branch-combine-never.ll
llvm/test/CodeGen/Mips/compact-branch-combine.ll
Modified:
llvm/lib/Target/Mips/Mips.td
llvm/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/lib/Target/Mips/MipsSubtarget.cpp
llvm/lib/Target/Mips/MipsSubtarget.h
llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll
llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 6c8d177093c76..8b0d87b5c5376 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -212,6 +212,10 @@ def FeatureStrictAlign
: SubtargetFeature<"strict-align", "StrictAlign", "true",
"Disable unaligned load store for r6">;
+def FeatureUseCompactBranches
+ : SubtargetFeature<"use-compact-branches", "UseCompactBranches", "true",
+ "Use compact branch instructions for MIPS32R6/MIPS64R6">;
+
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
@@ -220,6 +224,8 @@ def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">,
AssemblerPredicate<(all_of FeaturePTR64Bit)>;
def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">,
AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
+def UseCompactBranches : Predicate<"Subtarget->useCompactBranches()">,
+ AssemblerPredicate<(all_of FeatureUseCompactBranches)>;
//===----------------------------------------------------------------------===//
// HwModes
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 199d210f2f65b..308472e913225 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -1226,3 +1226,41 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
GPR32Opnd>,
ISA_MIPS32R6;
}
+
+// Combining branch and set instructions into one compact branch instruction
+let AdditionalPredicates = [NotInMicroMips, UseCompactBranches] in {
+ def : MipsPat<(brcond (i32 (setlt i32:$rs, 0)), bb:$offset),
+ (BLTZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setlt i32:$rs, 1)), bb:$offset),
+ (BLEZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setge i32:$rs, 0)), bb:$offset),
+ (BGEZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setge i32:$rs, 1)), bb:$offset),
+ (BGTZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setgt i32:$rs, 0)), bb:$offset),
+ (BGTZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setgt i32:$rs, -1)), bb:$offset),
+ (BGEZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setle i32:$rs, 0)), bb:$offset),
+ (BLEZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setle i32:$rs, -1)), bb:$offset),
+ (BLTZC GPR32Opnd:$rs, bb:$offset)>, ISA_MIPS32R6;
+
+ def : MipsPat<(brcond (i32 (setlt GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BLTC GPR32:$rs, GPR32:$rt, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setge GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BGEC GPR32:$rs, GPR32:$rt, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setgt GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BLTC GPR32:$rt, GPR32:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setle GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BGEC GPR32:$rt, GPR32:$rs, bb:$offset)>, ISA_MIPS32R6;
+
+ def : MipsPat<(brcond (i32 (setult GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BLTUC GPR32:$rs, GPR32:$rt, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setuge GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BGEUC GPR32:$rs, GPR32:$rt, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setugt GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BLTUC GPR32:$rt, GPR32:$rs, bb:$offset)>, ISA_MIPS32R6;
+ def : MipsPat<(brcond (i32 (setule GPR32:$rs, GPR32:$rt)), bb:$offset),
+ (BGEUC GPR32:$rt, GPR32:$rs, bb:$offset)>, ISA_MIPS32R6;
+}
diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
index 33132d9ede92a..47e3d48921155 100644
--- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -338,3 +338,41 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
GPR64Opnd>,
ISA_MIPS64R6;
}
+
+// Combining branch and set instructions into one compact branch instruction
+let AdditionalPredicates = [NotInMicroMips, UseCompactBranches] in {
+ def : MipsPat<(brcond (i32 (setlt i64:$rs, 0)), bb:$offset),
+ (BLTZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setlt i64:$rs, 1)), bb:$offset),
+ (BLEZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setge i64:$rs, 0)), bb:$offset),
+ (BGEZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setge i64:$rs, 1)), bb:$offset),
+ (BGTZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setgt i64:$rs, 0)), bb:$offset),
+ (BGTZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setgt i64:$rs, -1)), bb:$offset),
+ (BGEZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setle i64:$rs, 0)), bb:$offset),
+ (BLEZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setle i64:$rs, -1)), bb:$offset),
+ (BLTZC64 GPR64Opnd:$rs, bb:$offset)>, ISA_MIPS64R6;
+
+ def : MipsPat<(brcond (i32 (setlt GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BLTC64 GPR64:$rs, GPR64:$rt, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setge GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BGEC64 GPR64:$rs, GPR64:$rt, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setgt GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BLTC64 GPR64:$rt, GPR64:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setle GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BGEC64 GPR64:$rt, GPR64:$rs, bb:$offset)>, ISA_MIPS64R6;
+
+ def : MipsPat<(brcond (i32 (setult GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BLTUC64 GPR64:$rs, GPR64:$rt, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setuge GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BGEUC64 GPR64:$rs, GPR64:$rt, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setugt GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BLTUC64 GPR64:$rt, GPR64:$rs, bb:$offset)>, ISA_MIPS64R6;
+ def : MipsPat<(brcond (i32 (setule GPR64:$rs, GPR64:$rt)), bb:$offset),
+ (BGEUC64 GPR64:$rt, GPR64:$rs, bb:$offset)>, ISA_MIPS64R6;
+}
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index dfbbcbe602191..850d3b59be5de 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -77,25 +77,7 @@ static cl::opt<bool> DisableBackwardSearch(
cl::desc("Disallow MIPS delay filler to search backward."),
cl::Hidden);
-enum CompactBranchPolicy {
- CB_Never, ///< The policy 'never' may in some circumstances or for some
- ///< ISAs not be absolutely adhered to.
- CB_Optimal, ///< Optimal is the default and will produce compact branches
- ///< when delay slots cannot be filled.
- CB_Always ///< 'always' may in some circumstances may not be
- ///< absolutely adhered to there may not be a corresponding
- ///< compact form of a branch.
-};
-
-static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
- "mips-compact-branches", cl::Optional, cl::init(CB_Optimal),
- cl::desc("MIPS Specific: Compact branch policy."),
- cl::values(clEnumValN(CB_Never, "never",
- "Do not use compact branches if possible."),
- clEnumValN(CB_Optimal, "optimal",
- "Use compact branches where appropriate (default)."),
- clEnumValN(CB_Always, "always",
- "Always use compact branches if possible.")));
+extern cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy;
namespace {
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index b22647a851c2b..aef9382d3c1dc 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -27,6 +27,16 @@
using namespace llvm;
+cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
+ "mips-compact-branches", cl::Optional, cl::init(CB_Optimal),
+ cl::desc("MIPS Specific: Compact branch policy."),
+ cl::values(clEnumValN(CB_Never, "never",
+ "Do not use compact branches if possible."),
+ clEnumValN(CB_Optimal, "optimal",
+ "Use compact branches where appropriate (default)."),
+ clEnumValN(CB_Always, "always",
+ "Always use compact branches if possible.")));
+
#define DEBUG_TYPE "mips-subtarget"
#define GET_SUBTARGETINFO_TARGET_DESC
@@ -84,6 +94,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
UseIndirectJumpsHazard(false), StrictAlign(false),
+ UseCompactBranches(MipsCompactBranchPolicy != CB_Never),
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
InstrInfo(
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 0fbd425df1695..b09cfb3ac4a09 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -32,6 +32,16 @@
namespace llvm {
class StringRef;
+enum CompactBranchPolicy {
+ CB_Never, ///< The policy 'never' may in some circumstances or for some
+ ///< ISAs not be absolutely adhered to.
+ CB_Optimal, ///< Optimal is the default and will produce compact branches
+ ///< when appropriate.
+ CB_Always ///< 'always' may in some circumstances may not be
+ ///< absolutely adhered to, there may not be a corresponding
+ ///< compact form of a branch.
+};
+
class MipsTargetMachine;
class MipsSubtarget : public MipsGenSubtargetInfo {
@@ -201,6 +211,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
// Disable unaligned load store for r6.
bool StrictAlign;
+ // Use compact branch instructions for R6.
+ bool UseCompactBranches = true;
+
/// The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
Align stackAlignment;
@@ -336,6 +349,10 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
}
bool useSmallSection() const { return UseSmallSection; }
+ bool useCompactBranches() const {
+ return UseCompactBranches && hasMips32r6();
+ }
+
bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
bool useSoftFloat() const { return IsSoftFloat; }
diff --git a/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll b/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll
index ce0f2b0268d7b..18bba11575ddf 100644
--- a/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll
+++ b/llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll
@@ -17,13 +17,13 @@ define i32 @main(i32 signext %argc, ptr %argv) {
; CHECK-PIC: addiu
; CHECK-PIC: jrc
; CHECK-PIC: bc
-; CHECK-PIC: bnezc
+; CHECK-PIC: bltc
; CHECK-PIC: nop
; CHECK-PIC: bc
; CHECK-STATIC: bc
; CHECK-STATIC: j
-; CHECK-STATIC: bnezc
+; CHECK-STATIC: bltc
; CHECK-STATIC: nop
; CHECK-STATIC: j
entry:
diff --git a/llvm/test/CodeGen/Mips/compact-branch-combine-never.ll b/llvm/test/CodeGen/Mips/compact-branch-combine-never.ll
new file mode 100644
index 0000000000000..74e908d08248c
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/compact-branch-combine-never.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s --check-prefix=MIPS32R6
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -mips-compact-branches=never < %s | FileCheck %s --check-prefix=MIPS64R6
+
+;; Test checking we respect mips-compact-branches=never
+;; The patterns set + branch should be disabled and not emit compact branches
+
+define void @test_slt_never(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_slt_never:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: slt $1, $4, $5
+; MIPS32R6-NEXT: beqz $1, $BB0_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: $BB0_2: # %f
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: nop
+;
+; MIPS64R6-LABEL: test_slt_never:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $5, 0
+; MIPS64R6-NEXT: sll $2, $4, 0
+; MIPS64R6-NEXT: slt $1, $2, $1
+; MIPS64R6-NEXT: beqz $1, .LBB0_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jr $ra
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: .LBB0_2: # %f
+; MIPS64R6-NEXT: jr $ra
+; MIPS64R6-NEXT: nop
+ %c = icmp slt i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+define void @test_ult_never(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_ult_never:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: sltu $1, $4, $5
+; MIPS32R6-NEXT: beqz $1, $BB1_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: $BB1_2: # %f
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: nop
+;
+; MIPS64R6-LABEL: test_ult_never:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $5, 0
+; MIPS64R6-NEXT: sll $2, $4, 0
+; MIPS64R6-NEXT: sltu $1, $2, $1
+; MIPS64R6-NEXT: beqz $1, .LBB1_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jr $ra
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: .LBB1_2: # %f
+; MIPS64R6-NEXT: jr $ra
+; MIPS64R6-NEXT: nop
+ %c = icmp ult i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/Mips/compact-branch-combine.ll b/llvm/test/CodeGen/Mips/compact-branch-combine.ll
new file mode 100644
index 0000000000000..27a48e509deab
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/compact-branch-combine.ll
@@ -0,0 +1,463 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 < %s | FileCheck %s --check-prefix=MIPS32R6
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 < %s | FileCheck %s --check-prefix=MIPS64R6
+
+;; Each function is a single compare + branch
+;; Checking each pattern for compact branch is selected
+
+
+;; br + slt -> bgec
+define void @test_slt(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_slt:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bgec $4, $5, $BB0_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB0_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_slt:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $5, 0
+; MIPS64R6-NEXT: sll $2, $4, 0
+; MIPS64R6-NEXT: bgec $2, $1, .LBB0_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB0_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp slt i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sgt -> bgec
+define void @test_sgt(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_sgt:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bgec $5, $4, $BB1_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB1_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_sgt:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: sll $2, $5, 0
+; MIPS64R6-NEXT: bgec $2, $1, .LBB1_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB1_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sgt i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sge -> bltc
+define void @test_sge(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_sge:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bltc $4, $5, $BB2_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB2_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_sge:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $5, 0
+; MIPS64R6-NEXT: sll $2, $4, 0
+; MIPS64R6-NEXT: bltc $2, $1, .LBB2_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB2_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sge i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sle -> bltc
+define void @test_sle(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_sle:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bltc $5, $4, $BB3_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB3_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_sle:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: sll $2, $5, 0
+; MIPS64R6-NEXT: bltc $2, $1, .LBB3_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB3_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sle i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + ult -> bgeuc
+define void @test_ult(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_ult:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bgeuc $4, $5, $BB4_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB4_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_ult:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $5, 0
+; MIPS64R6-NEXT: sll $2, $4, 0
+; MIPS64R6-NEXT: bgeuc $2, $1, .LBB4_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB4_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp ult i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + ugt -> bgeuc
+define void @test_ugt(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_ugt:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bgeuc $5, $4, $BB5_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB5_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_ugt:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: sll $2, $5, 0
+; MIPS64R6-NEXT: bgeuc $2, $1, .LBB5_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB5_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp ugt i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + uge -> bltuc
+define void @test_uge(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_uge:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bltuc $4, $5, $BB6_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB6_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_uge:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $5, 0
+; MIPS64R6-NEXT: sll $2, $4, 0
+; MIPS64R6-NEXT: bltuc $2, $1, .LBB6_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB6_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp uge i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + ule -> bltuc
+define void @test_ule(i32 %a, i32 %b) {
+; MIPS32R6-LABEL: test_ule:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bltuc $5, $4, $BB7_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB7_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_ule:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: sll $2, $5, 0
+; MIPS64R6-NEXT: bltuc $2, $1, .LBB7_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB7_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp ule i32 %a, %b
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + slt rs,0 -> bltzc
+define void @test_lt_zero(i32 %a) {
+; MIPS32R6-LABEL: test_lt_zero:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bltzc $4, $BB8_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %f
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB8_2: # %t
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_lt_zero:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: bltzc $1, .LBB8_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %f
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB8_2: # %t
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp slt i32 %a, 0
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sgt rs,0 -> blezc
+define void @test_gt_zero(i32 %a) {
+; MIPS32R6-LABEL: test_gt_zero:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: blezc $4, $BB9_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB9_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_gt_zero:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: blezc $1, .LBB9_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB9_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sgt i32 %a, 0
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sle rs,0 -> bgtzc
+define void @test_le_zero(i32 %a) {
+; MIPS32R6-LABEL: test_le_zero:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bgtzc $4, $BB10_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB10_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_le_zero:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: bgtzc $1, .LBB10_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB10_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sle i32 %a, 0
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sge rs,0 -> bltzc
+define void @test_ge_zero(i32 %a) {
+; MIPS32R6-LABEL: test_ge_zero:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bltzc $4, $BB11_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB11_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_ge_zero:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: bltzc $1, .LBB11_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB11_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sge i32 %a, 0
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + slt rs,1 -> blezc
+define void @test_lt_one(i32 %a) {
+; MIPS32R6-LABEL: test_lt_one:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: blezc $4, $BB12_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %f
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB12_2: # %t
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_lt_one:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: blezc $1, .LBB12_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %f
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB12_2: # %t
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp slt i32 %a, 1
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sge rs,1 -> blezc
+define void @test_ge_one(i32 %a) {
+; MIPS32R6-LABEL: test_ge_one:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: blezc $4, $BB13_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB13_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_ge_one:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: blezc $1, .LBB13_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB13_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sge i32 %a, 1
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sgt rs,-1 -> bltzc
+define void @test_gt_minus1(i32 %a) {
+; MIPS32R6-LABEL: test_gt_minus1:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bltzc $4, $BB14_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB14_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_gt_minus1:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: bltzc $1, .LBB14_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB14_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sgt i32 %a, -1
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
+
+;; br + sle rs,-1 -> bgezc
+define void @test_le_minus1(i32 %a) {
+; MIPS32R6-LABEL: test_le_minus1:
+; MIPS32R6: # %bb.0:
+; MIPS32R6-NEXT: bgezc $4, $BB15_2
+; MIPS32R6-NEXT: nop
+; MIPS32R6-NEXT: # %bb.1: # %t
+; MIPS32R6-NEXT: jrc $ra
+; MIPS32R6-NEXT: $BB15_2: # %f
+; MIPS32R6-NEXT: jrc $ra
+;
+; MIPS64R6-LABEL: test_le_minus1:
+; MIPS64R6: # %bb.0:
+; MIPS64R6-NEXT: sll $1, $4, 0
+; MIPS64R6-NEXT: bgezc $1, .LBB15_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %t
+; MIPS64R6-NEXT: jrc $ra
+; MIPS64R6-NEXT: .LBB15_2: # %f
+; MIPS64R6-NEXT: jrc $ra
+ %c = icmp sle i32 %a, -1
+ br i1 %c, label %t, label %f
+t:
+ ret void
+f:
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
index 99efc5e8e4411..319ce9f8b57e2 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
@@ -24,7 +24,7 @@ sw.bb: ; preds = %entry
sw.bb1: ; preds = %entry, %entry
store volatile i32 2, ptr @boo, align 4
br label %sw.epilog
-; CHECK: bnezc
+; CHECK: bltuc
; CHECK-NEXT: nop
; CHECK-NEXT: # %bb.3
; CHECK-NEXT: j
diff --git a/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll b/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
index 3f6ac94801eb3..d08f618fa2e46 100644
--- a/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
+++ b/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
@@ -90,7 +90,7 @@ cond.false:
}
; CHECK-LABEL: test6:
-; CHECK: bnezc
+; CHECK: bltuc
; CHECK-NEXT: nop
define i32 @test6(i32 %a, i32 %b) {
@@ -106,7 +106,7 @@ cond.false:
}
; CHECK-LABEL: test7:
-; CHECK: beqzc
+; CHECK: bgeuc
; CHECK-NEXT: nop
define i32 @test7(i32 %a, i32 %b) {
@@ -122,7 +122,7 @@ cond.false:
}
; CHECK-LABEL: test8:
-; CHECK: bnezc
+; CHECK: bltuc
; CHECK-NEXT: nop
define i32 @test8(i32 %a, i32 %b) {
@@ -138,7 +138,7 @@ cond.false:
}
; CHECK-LABEL: test9:
-; CHECK: beqzc
+; CHECK: bgeuc
; CHECK-NEXT: nop
define i32 @test9(i32 %a, i32 %b) {
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