[llvm] [WebAssembly] Optimizes [zext](and 63|32) for shl, srl and sra with selectShiftMask (PR #170572)

[Luke Lau via llvm-commits]

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@@ -548,6 +557,49 @@ bool WebAssemblyDAGToDAGISel::SelectAddrOperands64(SDValue Op, SDValue &Offset,
   return SelectAddrOperands(MVT::i64, WebAssembly::CONST_I64, Op, Offset, Addr);
 }
 
+bool WebAssemblyDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
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lukel97 wrote:

I think on RISC-V there's an explicit ShiftWidth argument because on RV64 the type is always i64 even if you want to do a 32 bit shift. On webassembly both i32 and i64 are legal types. Can we get away without the ShiftWidth argument and instead get it from the size of N's type?

https://github.com/llvm/llvm-project/pull/170572