[llvm] 7a43921 - [AArch64][SVE] Fix -msve-vector-bits=256 fixed width vector crash (#171776)

[via llvm-commits]

Author: Matthew Devereau
Date: 2025-12-12T15:21:14Z
New Revision: 7a43921af824ff39a4b9114dc9624f4ff008376d

URL: https://github.com/llvm/llvm-project/commit/7a43921af824ff39a4b9114dc9624f4ff008376d
DIFF: https://github.com/llvm/llvm-project/commit/7a43921af824ff39a4b9114dc9624f4ff008376d.diff

LOG: [AArch64][SVE] Fix -msve-vector-bits=256 fixed width vector crash (#171776)

This adds tests for and fixes an issue where v8bf16 ISD::FP_ROUND v8f32
cannot be lowered when -msve-vector-bits=256.

Added: 
    llvm/test/CodeGen/AArch64/sve-fixed-length-fptrunc.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 1ade1df88f010..288a285276ce1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1878,7 +1878,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       // 128bit results imply a bigger than NEON input.
       for (auto VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
         setOperationAction(ISD::TRUNCATE, VT, Custom);
-      for (auto VT : {MVT::v8f16, MVT::v4f32})
+      for (auto VT : {MVT::v8f16, MVT::v4f32, MVT::v8bf16})
         setOperationAction(ISD::FP_ROUND, VT, Custom);
 
       // These operations are not supported on NEON but SVE can do them.

diff  --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fptrunc.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fptrunc.ll
new file mode 100644
index 0000000000000..65c8dc0ad59dc
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fptrunc.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+
+define <8 x bfloat> @fptrunc_v8bf16(<8 x float> %a) #0 {
+; CHECK-LABEL: fptrunc_v8bf16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d, vl2
+; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    bfcvt z0.h, p0/m, z0.s
+; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %fpt = fptrunc <8 x float> %a to <8 x bfloat>
+  ret <8 x bfloat> %fpt
+}
+
+define <8 x half> @fptrunc_v8f16(<8 x float> %a) #0 {
+; CHECK-LABEL: fptrunc_v8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d, vl2
+; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
+; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %fpt = fptrunc <8 x float> %a to <8 x half>
+  ret <8 x half> %fpt
+}
+
+attributes #0 = { vscale_range(2,2) "target-features"="+bf16,+sve" }