[llvm] [SDAG] Fix incorrect usage of VECREDUCE_ADD (PR #171459)

[Paul Walker via llvm-commits]

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@@ -2663,8 +2663,10 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_COMPRESS(SDNode *N, SDValue &Lo,
       MF, cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex());
 
   // We store LoVec and then insert HiVec starting at offset=|1s| in LoMask.
-  SDValue WideMask =
-      DAG.getNode(ISD::ZERO_EXTEND, DL, LoMask.getValueType(), LoMask);
+  EVT WideMaskVT =
+      EVT::getVectorVT(*DAG.getContext(), MVT::i32,
+                       LoMask.getValueType().getVectorElementCount());
+  SDValue WideMask = DAG.getNode(ISD::ZERO_EXTEND, DL, WideMaskVT, LoMask);
   SDValue Offset = DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, WideMask);
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paulwalker-arm wrote:

I think the key here is what `SplitMask` will return. I guess you could start with an "is a vector of i1s assert" and see if anything falls out.

https://github.com/llvm/llvm-project/pull/171459