[llvm] [SDAG] Fix incorrect usage of VECREDUCE_ADD (PR #171459)

[Benjamin Maxwell via llvm-commits]

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@@ -2663,8 +2663,10 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_COMPRESS(SDNode *N, SDValue &Lo,
       MF, cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex());
 
   // We store LoVec and then insert HiVec starting at offset=|1s| in LoMask.
-  SDValue WideMask =
-      DAG.getNode(ISD::ZERO_EXTEND, DL, LoMask.getValueType(), LoMask);
+  EVT WideMaskVT =
+      EVT::getVectorVT(*DAG.getContext(), MVT::i32,
+                       LoMask.getValueType().getVectorElementCount());
+  SDValue WideMask = DAG.getNode(ISD::ZERO_EXTEND, DL, WideMaskVT, LoMask);
   SDValue Offset = DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, WideMask);
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MacDue wrote:

I'm not 100% sure (I think in our case it's `i1`s here), but it looks like the mask could be promoted:

https://github.com/llvm/llvm-project/blob/234c41413fba1655bb441dfe11a0c9d2414466de/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp#L2601-L2609

So it's likely assuming `ZeroOrOneBooleanContent`. 

https://github.com/llvm/llvm-project/pull/171459