[llvm] [LangRef] Fix inequalities and add examples for `loop.dependence.*.mask` (PR #170861)

Sander de Smalen via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 12 03:59:13 PST 2025


================
@@ -24551,6 +24589,32 @@ Examples:
       [...]
       %vecB = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(ptr align 4 %ptrB, <4 x i1> %loop.dependence.mask, <4 x i32> poison)
 
+      ; For the above example, consider the following cases:
+      ;
+      ; 1. ptrA == ptrB
+      ;
+      ;  store = <0,1,2,3>       ; array[i] = store;
+      ;   load = <0,1,2,3>       ; uint32_t load = array[i];
+      ;
+      ; This results in a all-true mask. There is no conflict.
+      ;
+      ; 2. ptrB - ptrA = 2 * elementSize
+      ;
+      ;  store =  <0,1,2,3>      ; array[i] = store;
+      ;   load =      <0,1,2,3>  ; uint32_t load = array[i+2];
+      ;
+      ; This results in a mask with the first two lanes active. In this case,
+      ; only two lanes can be written without overwriting values yet to be read.
+      ;
+      ; 3. ptrB - ptrA = -2 * elementSize
+      ;
+      ;  store =      <0,1,2,3>  ; array[i+2] = store;
+      ;   load =  <0,1,2,3>      ; uint32_t load = array[i];
+      ;
+      ; This also results in a mask with the first two lanes active. This could
+      ; result in a hazard if the store is scheduled after the load, so we only
+      ; consider the first two lanes to be readable.
----------------
sdesmalen-arm wrote:

That captures it correctly, although in this example I would remove the word hazard and simply say that with an all-true mask the load cannot be started before finishing the store as this may result in a pipeline stall.

https://github.com/llvm/llvm-project/pull/170861


More information about the llvm-commits mailing list