[llvm] [SDAG] Shrink (abd? (?ext x) (?ext y)) (PR #171865)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 12 03:55:09 PST 2025
https://github.com/natanelh-mobileye updated https://github.com/llvm/llvm-project/pull/171865
>From 5840f2cf47c67d3157b7d03a169e778f6dc9e3a5 Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Thu, 11 Dec 2025 18:35:26 +0200
Subject: [PATCH 1/7] [SDAG] Shrink (abds (sext x) (sext y))
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 16 ++++++++-
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 33 +++++++++++++++++++
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6a99d4e29b64f..0e44895f957fe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5771,7 +5771,7 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
if (N0 == N1)
return DAG.getConstant(0, DL, VT);
- SDValue X;
+ SDValue X, Y;
// fold (abds x, 0) -> abs x
if (sd_match(N, m_c_BinOp(ISD::ABDS, m_Value(X), m_Zero())) &&
@@ -5787,6 +5787,20 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
+ // fold (abds (sext x), (sext y)) -> (zext (abds x, y))
+ if (sd_match(N,
+ m_c_BinOp(ISD::ABDS, m_SExt(m_Value(X)), m_SExt(m_Value(Y)))) &&
+ X.getValueType() == Y.getValueType()) {
+ EVT SmallVT = X.getScalarValueSizeInBits() > Y.getScalarValueSizeInBits()
+ ? X.getValueType()
+ : Y.getValueType();
+ if (!LegalOperations || hasOperation(ISD::ABDS, SmallVT)) {
+ SDValue SmallABD = DAG.getNode(N->getOpcode(), DL, SmallVT, {X, Y});
+ SDValue ZExted = DAG.getZExtOrTrunc(SmallABD, DL, VT);
+ return ZExted;
+ }
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index a3f4722e14406..15e55cd852feb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1,6 +1,39 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s -check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+define <16 x i16> @sabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: sabd16b_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sabd.16b v0, v0, v1
+; CHECK-SD-NEXT: ushll2.8h v1, v0, #0
+; CHECK-SD-NEXT: ushll.8h v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sabd16b_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v2, v0, #0
+; CHECK-GI-NEXT: sshll.8h v3, v1, #0
+; CHECK-GI-NEXT: sshll2.8h v4, v0, #0
+; CHECK-GI-NEXT: sshll2.8h v5, v1, #0
+; CHECK-GI-NEXT: ssubl.8h v6, v0, v1
+; CHECK-GI-NEXT: ssubl2.8h v7, v0, v1
+; CHECK-GI-NEXT: cmgt.8h v2, v3, v2
+; CHECK-GI-NEXT: cmgt.8h v3, v5, v4
+; CHECK-GI-NEXT: ssubl.8h v4, v1, v0
+; CHECK-GI-NEXT: ssubl2.8h v1, v1, v0
+; CHECK-GI-NEXT: mov.16b v0, v2
+; CHECK-GI-NEXT: bif.16b v1, v7, v3
+; CHECK-GI-NEXT: bsl.16b v0, v4, v6
+; CHECK-GI-NEXT: ret
+ %aext = sext <16 x i8> %a to <16 x i16>
+ %bext = sext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp slt <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl8h:
>From c25cbd1ffd2b14ad35358ba59336aae16e39610a Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Thu, 11 Dec 2025 19:11:19 +0200
Subject: [PATCH 2/7] Move test to the end
---
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 66 ++++++++++++-------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index 15e55cd852feb..acf46c600ba33 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1,39 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s -check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-define <16 x i16> @sabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-SD-LABEL: sabd16b_i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sabd.16b v0, v0, v1
-; CHECK-SD-NEXT: ushll2.8h v1, v0, #0
-; CHECK-SD-NEXT: ushll.8h v0, v0, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: sabd16b_i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll.8h v2, v0, #0
-; CHECK-GI-NEXT: sshll.8h v3, v1, #0
-; CHECK-GI-NEXT: sshll2.8h v4, v0, #0
-; CHECK-GI-NEXT: sshll2.8h v5, v1, #0
-; CHECK-GI-NEXT: ssubl.8h v6, v0, v1
-; CHECK-GI-NEXT: ssubl2.8h v7, v0, v1
-; CHECK-GI-NEXT: cmgt.8h v2, v3, v2
-; CHECK-GI-NEXT: cmgt.8h v3, v5, v4
-; CHECK-GI-NEXT: ssubl.8h v4, v1, v0
-; CHECK-GI-NEXT: ssubl2.8h v1, v1, v0
-; CHECK-GI-NEXT: mov.16b v0, v2
-; CHECK-GI-NEXT: bif.16b v1, v7, v3
-; CHECK-GI-NEXT: bsl.16b v0, v4, v6
-; CHECK-GI-NEXT: ret
- %aext = sext <16 x i8> %a to <16 x i16>
- %bext = sext <16 x i8> %b to <16 x i16>
- %abdiff = sub nsw <16 x i16> %aext, %bext
- %abcmp = icmp slt <16 x i16> %aext, %bext
- %ababs = sub nsw <16 x i16> %bext, %aext
- %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
- %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
- ret <16 x i16> %absel
-}
define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl8h:
@@ -1985,3 +1952,36 @@ define <8 x i16> @pr88784_fixed(<8 x i8> %l0, <8 x i8> %l1, <8 x i16> %l2) {
ret <8 x i16> %l9
}
+define <16 x i16> @sabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: sabd16b_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sabd.16b v0, v0, v1
+; CHECK-SD-NEXT: ushll2.8h v1, v0, #0
+; CHECK-SD-NEXT: ushll.8h v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sabd16b_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v2, v0, #0
+; CHECK-GI-NEXT: sshll.8h v3, v1, #0
+; CHECK-GI-NEXT: sshll2.8h v4, v0, #0
+; CHECK-GI-NEXT: sshll2.8h v5, v1, #0
+; CHECK-GI-NEXT: ssubl.8h v6, v0, v1
+; CHECK-GI-NEXT: ssubl2.8h v7, v0, v1
+; CHECK-GI-NEXT: cmgt.8h v2, v3, v2
+; CHECK-GI-NEXT: cmgt.8h v3, v5, v4
+; CHECK-GI-NEXT: ssubl.8h v4, v1, v0
+; CHECK-GI-NEXT: ssubl2.8h v1, v1, v0
+; CHECK-GI-NEXT: mov.16b v0, v2
+; CHECK-GI-NEXT: bif.16b v1, v7, v3
+; CHECK-GI-NEXT: bsl.16b v0, v4, v6
+; CHECK-GI-NEXT: ret
+ %aext = sext <16 x i8> %a to <16 x i16>
+ %bext = sext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp slt <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
>From 2968cd21516f91072fa3308061c8a3d57409931c Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Thu, 11 Dec 2025 19:25:27 +0200
Subject: [PATCH 3/7] abdu test
---
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 37 +++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index acf46c600ba33..9860f36773c28 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1985,3 +1985,40 @@ define <16 x i16> @sabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
%reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
ret <16 x i16> %absel
}
+
+define <16 x i16> @uabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: uabd16b_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll.8h v2, v0, #0
+; CHECK-SD-NEXT: ushll2.8h v0, v0, #0
+; CHECK-SD-NEXT: ushll.8h v3, v1, #0
+; CHECK-SD-NEXT: ushll2.8h v1, v1, #0
+; CHECK-SD-NEXT: uabd.8h v1, v0, v1
+; CHECK-SD-NEXT: uabd.8h v0, v2, v3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uabd16b_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll.8h v2, v0, #0
+; CHECK-GI-NEXT: ushll.8h v3, v1, #0
+; CHECK-GI-NEXT: ushll2.8h v4, v0, #0
+; CHECK-GI-NEXT: ushll2.8h v5, v1, #0
+; CHECK-GI-NEXT: usubl.8h v6, v0, v1
+; CHECK-GI-NEXT: usubl2.8h v7, v0, v1
+; CHECK-GI-NEXT: cmhi.8h v2, v3, v2
+; CHECK-GI-NEXT: cmhi.8h v3, v5, v4
+; CHECK-GI-NEXT: usubl.8h v4, v1, v0
+; CHECK-GI-NEXT: usubl2.8h v1, v1, v0
+; CHECK-GI-NEXT: mov.16b v0, v2
+; CHECK-GI-NEXT: bif.16b v1, v7, v3
+; CHECK-GI-NEXT: bsl.16b v0, v4, v6
+; CHECK-GI-NEXT: ret
+ %aext = zext <16 x i8> %a to <16 x i16>
+ %bext = zext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp ult <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
>From e79ac7029a62688adc4c8484c3733ab2b860c7b9 Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Thu, 11 Dec 2025 19:45:49 +0200
Subject: [PATCH 4/7] zext code, extend both to common type
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 13 ++++++++-----
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 9 +++------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0e44895f957fe..cbe084e9194a2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5787,15 +5787,18 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
- // fold (abds (sext x), (sext y)) -> (zext (abds x, y))
+ // fold (abds (?ext x), (?ext y)) -> (zext (abd? x, y))
if (sd_match(N,
- m_c_BinOp(ISD::ABDS, m_SExt(m_Value(X)), m_SExt(m_Value(Y)))) &&
- X.getValueType() == Y.getValueType()) {
+ m_c_BinOp(ISD::ABDU, m_ZExt(m_Value(X)), m_ZExt(m_Value(Y)))) ||
+ sd_match(N,
+ m_c_BinOp(ISD::ABDS, m_SExt(m_Value(X)), m_SExt(m_Value(Y))))) {
EVT SmallVT = X.getScalarValueSizeInBits() > Y.getScalarValueSizeInBits()
? X.getValueType()
: Y.getValueType();
- if (!LegalOperations || hasOperation(ISD::ABDS, SmallVT)) {
- SDValue SmallABD = DAG.getNode(N->getOpcode(), DL, SmallVT, {X, Y});
+ auto ExtedX = DAG.getExtOrTrunc(N0->getOpcode(), X, X, SmallVT);
+ auto ExtedY = DAG.getExtOrTrunc(N0->getOpcode(), Y, Y, SmallVT);
+ if (!LegalOperations || hasOperation(Opcode, SmallVT)) {
+ SDValue SmallABD = DAG.getNode(Opcode, DL, SmallVT, {ExtedX, ExtedY});
SDValue ZExted = DAG.getZExtOrTrunc(SmallABD, DL, VT);
return ZExted;
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index 9860f36773c28..bcd63149c7ffa 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1989,12 +1989,9 @@ define <16 x i16> @sabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
define <16 x i16> @uabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
; CHECK-SD-LABEL: uabd16b_i16:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll.8h v2, v0, #0
-; CHECK-SD-NEXT: ushll2.8h v0, v0, #0
-; CHECK-SD-NEXT: ushll.8h v3, v1, #0
-; CHECK-SD-NEXT: ushll2.8h v1, v1, #0
-; CHECK-SD-NEXT: uabd.8h v1, v0, v1
-; CHECK-SD-NEXT: uabd.8h v0, v2, v3
+; CHECK-SD-NEXT: uabd.16b v0, v0, v1
+; CHECK-SD-NEXT: ushll2.8h v1, v0, #0
+; CHECK-SD-NEXT: ushll.8h v0, v0, #0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: uabd16b_i16:
>From eea608778a5ffe1c6487fe8eecdbc30f291d8d9b Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Thu, 11 Dec 2025 20:05:12 +0200
Subject: [PATCH 5/7] diff types test
---
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 62 +++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index bcd63149c7ffa..c903cee802c32 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -2019,3 +2019,65 @@ define <16 x i16> @uabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
%reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
ret <16 x i16> %absel
}
+
+define <16 x i16> @sabd16b_i16_ext(<16 x i16> %aext, <16 x i8> %b) {
+; CHECK-SD-LABEL: sabd16b_i16_ext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll.8h v3, v2, #0
+; CHECK-SD-NEXT: sshll2.8h v2, v2, #0
+; CHECK-SD-NEXT: sabd.8h v1, v1, v2
+; CHECK-SD-NEXT: sabd.8h v0, v0, v3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sabd16b_i16_ext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v3, v2, #0
+; CHECK-GI-NEXT: sshll2.8h v4, v2, #0
+; CHECK-GI-NEXT: ssubw.8h v5, v0, v2
+; CHECK-GI-NEXT: ssubw2.8h v2, v1, v2
+; CHECK-GI-NEXT: cmgt.8h v6, v3, v0
+; CHECK-GI-NEXT: cmgt.8h v7, v4, v1
+; CHECK-GI-NEXT: sub.8h v0, v3, v0
+; CHECK-GI-NEXT: sub.8h v1, v4, v1
+; CHECK-GI-NEXT: bif.16b v0, v5, v6
+; CHECK-GI-NEXT: bif.16b v1, v2, v7
+; CHECK-GI-NEXT: ret
+ %bext = sext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp slt <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
+
+define <16 x i16> @uabd16b_i16_ext(<16 x i16> %aext, <16 x i8> %b) {
+; CHECK-SD-LABEL: uabd16b_i16_ext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll.8h v3, v2, #0
+; CHECK-SD-NEXT: ushll2.8h v2, v2, #0
+; CHECK-SD-NEXT: uabd.8h v1, v1, v2
+; CHECK-SD-NEXT: uabd.8h v0, v0, v3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uabd16b_i16_ext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll.8h v3, v2, #0
+; CHECK-GI-NEXT: ushll2.8h v4, v2, #0
+; CHECK-GI-NEXT: usubw.8h v5, v0, v2
+; CHECK-GI-NEXT: usubw2.8h v2, v1, v2
+; CHECK-GI-NEXT: cmhi.8h v6, v3, v0
+; CHECK-GI-NEXT: cmhi.8h v7, v4, v1
+; CHECK-GI-NEXT: sub.8h v0, v3, v0
+; CHECK-GI-NEXT: sub.8h v1, v4, v1
+; CHECK-GI-NEXT: bif.16b v0, v5, v6
+; CHECK-GI-NEXT: bif.16b v1, v2, v7
+; CHECK-GI-NEXT: ret
+ %bext = zext <16 x i8> %b to <16 x i16>
+ %abdiff = sub nsw <16 x i16> %aext, %bext
+ %abcmp = icmp ult <16 x i16> %aext, %bext
+ %ababs = sub nsw <16 x i16> %bext, %aext
+ %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+ %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+ ret <16 x i16> %absel
+}
>From b909b52b95882d4d17f4a2c0134caa47ec0949e1 Mon Sep 17 00:00:00 2001
From: natanelh-mobileye <natanelh at mobileye.com>
Date: Thu, 11 Dec 2025 21:39:32 +0200
Subject: [PATCH 6/7] remove reduce_add
---
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index c903cee802c32..4d5542ab2d2e6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -2016,7 +2016,6 @@ define <16 x i16> @uabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
%abcmp = icmp ult <16 x i16> %aext, %bext
%ababs = sub nsw <16 x i16> %bext, %aext
%absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
- %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
ret <16 x i16> %absel
}
>From 92fa049719785ff906e10aadd36e4d90d7af25e7 Mon Sep 17 00:00:00 2001
From: Natanel Hofshi <natanel.hofshi at mobileye.com>
Date: Fri, 12 Dec 2025 13:54:18 +0200
Subject: [PATCH 7/7] Move Ext inside
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index cbe084e9194a2..35350491149be 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5795,9 +5795,9 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
EVT SmallVT = X.getScalarValueSizeInBits() > Y.getScalarValueSizeInBits()
? X.getValueType()
: Y.getValueType();
- auto ExtedX = DAG.getExtOrTrunc(N0->getOpcode(), X, X, SmallVT);
- auto ExtedY = DAG.getExtOrTrunc(N0->getOpcode(), Y, Y, SmallVT);
if (!LegalOperations || hasOperation(Opcode, SmallVT)) {
+ SDValue ExtedX = DAG.getExtOrTrunc(X, SDLoc(X), SmallVT, N0->getOpcode());
+ SDValue ExtedY = DAG.getExtOrTrunc(Y, SDLoc(Y), SmallVT, N0->getOpcode());
SDValue SmallABD = DAG.getNode(Opcode, DL, SmallVT, {ExtedX, ExtedY});
SDValue ZExted = DAG.getZExtOrTrunc(SmallABD, DL, VT);
return ZExted;
More information about the llvm-commits
mailing list