[llvm] [DAG] Fold logic of zero-checks to multiplication for MinSize (PR #171805)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 11 20:56:42 PST 2025
================
@@ -6648,6 +6649,58 @@ static unsigned getMinMaxOpcodeForFP(SDValue Operand1, SDValue Operand2,
return ISD::DELETED_NODE;
}
+// Fold the following patterns for small integers in -Oz mode.
+// (X == 0) || (Y == 0) --> (X * Y) == 0
+// (X != 0) && (Y != 0) --> (X * Y) != 0
+SDValue DAGCombiner::foldLogicSetCCToMul(SDNode *N, const SDLoc &DL) {
+ if (!DAG.getMachineFunction().getFunction().hasMinSize())
+ return SDValue();
+
+ unsigned Opcode = N->getOpcode();
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+
+ ISD::CondCode ExpectedCC;
+ if (Opcode == ISD::OR) {
+ ExpectedCC = ISD::SETEQ;
+ } else if (Opcode == ISD::AND) {
+ ExpectedCC = ISD::SETNE;
+ } else {
+ return SDValue();
+ }
+
+ if (N0.getOpcode() != ISD::SETCC || N1.getOpcode() != ISD::SETCC)
+ return SDValue();
+
+ SDValue A = N0.getOperand(0);
+ SDValue B = N1.getOperand(0);
+ SDValue C0 = N0.getOperand(1);
+ SDValue C1 = N1.getOperand(1);
+ ISD::CondCode CC0 = cast<CondCodeSDNode>(N0.getOperand(2))->get();
+ ISD::CondCode CC1 = cast<CondCodeSDNode>(N1.getOperand(2))->get();
+
+ if (CC0 != ExpectedCC || CC1 != ExpectedCC ||
+ !A.getValueType().isScalarInteger() ||
+ A.getValueType() != B.getValueType() || !isNullConstant(C0) ||
+ !isNullConstant(C1))
+ return SDValue();
+
+ unsigned BitWidth = A.getValueSizeInBits();
+ KnownBits KnownA = DAG.computeKnownBits(A);
+ KnownBits KnownB = DAG.computeKnownBits(B);
+
+ if (KnownA.countMaxActiveBits() + KnownB.countMaxActiveBits() > BitWidth)
+ return SDValue();
+
+ SDNodeFlags Flags;
+ Flags.setNoUnsignedWrap(true);
+ Flags.setNoSignedWrap(true);
+
+ SDValue Mul = DAG.getNode(ISD::MUL, DL, A.getValueType(), A, B, Flags);
----------------
TelGome wrote:
I’ve added the legality check and updated the patch.
https://github.com/llvm/llvm-project/pull/171805
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