[llvm] [RISCV] Implement RVV scheduling model for andes 45 series processor. (PR #167821)

[Jim Lin via llvm-commits]

tclin914 wrote:

> could you split this PR into smaller patches? The RISCVSchedAndes45.td alone has over a thousand lines of changes. SpacemitX60 did a similar thing to split it into smaller PRs

Hi @mshockwave ,

I file another PR https://github.com/llvm/llvm-project/pull/171954 to pre-commit the scheduling info for Andes45. 
And then I will have more follow-up PRs with smaller changes. Thanks.

https://github.com/llvm/llvm-project/pull/167821