[llvm] [RISCV] Pre-commit RVV instructions to the Ands45 scheduling model and tests (PR #171954)
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 11 19:13:30 PST 2025
https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/171954
This is like what spacemit x60 did in
https://github.com/llvm/llvm-project/commit/c4d4e761ef27d6dd27323cf3efa506db5e9e3457.
>From 03d274ec3d2b477c5602d7079f0296d5fe987641 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 25 Jun 2025 16:18:39 +0800
Subject: [PATCH] [RISCV] Pre-commit RVV instructions to the Ands45 scheduling
model and tests
This is like what spacemit x60 did in
https://github.com/llvm/llvm-project/commit/c4d4e761ef27d6dd27323cf3efa506db5e9e3457.
---
llvm/lib/Target/RISCV/RISCVSchedAndes45.td | 551 +-
llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s | 40 +-
llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s | 98 +-
.../llvm-mca/RISCV/Andes45/rvv-arithmetic.s | 6837 +++++++++++++++++
.../llvm-mca/RISCV/Andes45/rvv-bitwise.s | 4345 +++++++++++
.../llvm-mca/RISCV/Andes45/rvv-comparison.s | 2721 +++++++
.../llvm-mca/RISCV/Andes45/rvv-conversion.s | 1774 +++++
.../tools/llvm-mca/RISCV/Andes45/rvv-fma.s | 2202 ++++++
.../tools/llvm-mca/RISCV/Andes45/rvv-fp.s | 5616 ++++++++++++++
.../tools/llvm-mca/RISCV/Andes45/rvv-mask.s | 1881 +++++
.../tools/llvm-mca/RISCV/Andes45/rvv-minmax.s | 1125 +++
.../llvm-mca/RISCV/Andes45/rvv-mul-div.s | 3001 ++++++++
.../llvm-mca/RISCV/Andes45/rvv-permutation.s | 3521 +++++++++
.../llvm-mca/RISCV/Andes45/rvv-reduction.s | 1841 +++++
.../llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s | 557 ++
.../llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s | 331 +
.../llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s | 4742 ++++++++++++
.../llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s | 603 ++
18 files changed, 41723 insertions(+), 63 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index 8cf15fa26e22d..d5f523711100a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -8,7 +8,20 @@
//===----------------------------------------------------------------------===//
-// FIXME: Implement sheduling model for V and other extensions.
+// The worst case LMUL is the largest LMUL.
+class Andes45IsWorstCaseMX<string mx, list<string> MxList> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+// The worst case is the largest LMUL with the smallest SEW.
+class Andes45IsWorstCaseMXSEW<string mx, int sew, list<string> MxList,
+ bit isF = 0> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ defvar SSEW = SmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
def Andes45Model : SchedMachineModel {
let MicroOpBufferSize = 0; // Andes45 is in-order processor
let IssueWidth = 2; // 2 micro-ops dispatched per cycle
@@ -32,6 +45,15 @@ let SchedModel = Andes45Model in {
// - Floating Point Divide / SQRT Unit (FDIV)
// - Floating Point Move Unit (FMV)
// - Floating Point Misc Unit (FMISC)
+//
+// Andes 45 series VPU
+// - Vector Arithmetic and Logical Unit (VALU)
+// - Vector Multiply Accumulate Unit (VMAC)
+// - Vector Divide Unit (VDIV)
+// - Vector Permutation Unit (VPERMUT)
+// - Vector Mask Unit (VMASK)
+// - Vector Floating-Point Miscellaneous Unit (VFMIS)
+// - Vector Floating-Point Divide Unit (VFDIV)
//===----------------------------------------------------------------------===//
let BufferSize = 0 in {
@@ -44,6 +66,15 @@ def Andes45FMAC : ProcResource<1>;
def Andes45FDIV : ProcResource<1>;
def Andes45FMV : ProcResource<1>;
def Andes45FMISC : ProcResource<1>;
+
+def Andes45VALU : ProcResource<1>;
+def Andes45VMAC : ProcResource<1>;
+def Andes45VFMIS : ProcResource<1>;
+def Andes45VPERMUT : ProcResource<1>;
+def Andes45VDIV : ProcResource<1>;
+def Andes45VFDIV : ProcResource<1>;
+def Andes45VMASK : ProcResource<1>;
+def Andes45VLSU : ProcResource<1>;
}
// Integer arithmetic and logic
@@ -333,10 +364,526 @@ def : ReadAdvance<ReadSingleBit, 0>;
def : ReadAdvance<ReadSingleBitImm, 0>;
def : ReadAdvance<ReadCSR, 0>;
+// RVV Scheduling
+
+// 6. Configuration-Setting Instructions
+def : WriteRes<WriteVSETVLI, [Andes45CSR]>;
+def : WriteRes<WriteVSETIVLI, [Andes45CSR]>;
+def : WriteRes<WriteVSETVL, [Andes45CSR]>;
+
+// 7. Vector Loads and Stores
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ // Unit-stride loads and stores
+ defm "" : LMULWriteResMX<"WriteVLDE", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTE", [Andes45VLSU], mx, IsWorstCase>;
+
+ // Mask loads and stores
+ defm "" : LMULWriteResMX<"WriteVLDM", [Andes45VLSU], mx, IsWorstCase=!eq(mx, "M1")>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [Andes45VLSU], mx, IsWorstCase=!eq(mx, "M1")>;
+
+ // Strided and indexed loads and stores
+ foreach eew = [8, 16, 32, 64] in {
+ defm "" : LMULWriteResMX<"WriteVLDS" # eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [Andes45VLSU], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVSTS" # eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [Andes45VLSU], mx, IsWorstCase>;
+ }
+}
+
+// Segmented loads and stores
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ // Unit-stride segmented
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+
+ // Strided/indexed segmented
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+
+ // Indexed segmented
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" #eew, [Andes45VLSU], mx, IsWorstCase>;
+ }
+ }
+}
+
+// Whole register move/load/store
+foreach LMul = [1, 2, 4, 8] in {
+ def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [Andes45VLSU]>;
+ def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [Andes45VLSU]>;
+
+ def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [Andes45VPERMUT]>;
+}
+
+// 11. Vector Integer Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defm "" : LMULWriteResMX<"WriteVIALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVExtV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [Andes45VALU], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVShiftV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [Andes45VALU], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVIMulV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulX", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [Andes45VMAC], mx, IsWorstCase>;
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [Andes45VMAC], mx, IsWorstCase>;
+}
+
+// Vector Integer Division and Remainder
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [Andes45VDIV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [Andes45VDIV], mx, sew, IsWorstCase>;
+ }
+}
+
+// Narrowing Shift
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [Andes45VALU], mx, IsWorstCase>;
+}
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defm "" : LMULWriteResMX<"WriteVSALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [Andes45VALU], mx, IsWorstCase>;
+}
+
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ defm "" : LMULWriteResMX<"WriteVNClipV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [Andes45VALU], mx, IsWorstCase>;
+}
+
+// 13. Vector Floating-Point Instructions
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [Andes45VFMIS], mx, sew, IsWorstCase>;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [Andes45VFMIS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [Andes45VFMIS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFClassV", [Andes45VFMIS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMergeV", [Andes45VFMIS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMovV", [Andes45VFMIS], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [Andes45VFMIS], mx, IsWorstCase>;
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFW in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListFW>.c;
+
+ defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [Andes45VFMIS], mx, IsWorstCase>;
+}
+
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+}
+
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [Andes45VFMIS], mx, IsWorstCase>;
+}
+
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+}
+
+// Vector Floating-Point Division and Square Root
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ }
+}
+
+// 14. Vector Reduction Operations
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [Andes45VALU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [Andes45VALU], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListWRed in {
+ foreach sew = SchedSEWSet<mx, 0, 1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [Andes45VALU], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFWRed in {
+ foreach sew = SchedSEWSet<mx, 1, 1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
+
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [Andes45VMAC], mx, sew, IsWorstCase>;
+ }
+}
+
+// 15. Vector Mask Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defm "" : LMULWriteResMX<"WriteVMALUV", [Andes45VMASK], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMPopV", [Andes45VMASK], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [Andes45VMASK], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [Andes45VMASK], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVIotaV", [Andes45VMASK], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [Andes45VMASK], mx, IsWorstCase>;
+}
+
+// 16. Vector Permutation Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defm "" : LMULWriteResMX<"WriteVSlideI", [Andes45VPERMUT], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVISlide1X", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1F", [Andes45VPERMUT], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [Andes45VPERMUT], mx, IsWorstCase>;
+}
+
+def : WriteRes<WriteVMovXS, [Andes45VPERMUT]>;
+def : WriteRes<WriteVMovSX, [Andes45VPERMUT]>;
+
+def : WriteRes<WriteVMovFS, [Andes45VPERMUT]>;
+def : WriteRes<WriteVMovSF, [Andes45VPERMUT]>;
+
+// Gather and Compress
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [Andes45VPERMUT], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [Andes45VPERMUT], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [Andes45VPERMUT], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRGatherVI", [Andes45VPERMUT], mx, IsWorstCase>;
+}
+
+// Others
+def : WriteRes<WriteRdVLENB, [Andes45CSR]>;
+
+// 6. Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 0>;
+def : ReadAdvance<ReadVSETVL, 0>;
+
+// 7. Vector Loads and Stores
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVST1R, 0>;
+def : ReadAdvance<ReadVST2R, 0>;
+def : ReadAdvance<ReadVST4R, 0>;
+def : ReadAdvance<ReadVST8R, 0>;
+
+// 11. Vector Integer Arithmetic Instructions
+defm : LMULReadAdvance<"ReadVIALUV", 0>;
+defm : LMULReadAdvance<"ReadVIALUX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm : LMULReadAdvance<"ReadVExtV", 0>;
+defm : LMULReadAdvance<"ReadVICALUV", 0>;
+defm : LMULReadAdvance<"ReadVICALUX", 0>;
+defm : LMULReadAdvance<"ReadVShiftV", 0>;
+defm : LMULReadAdvance<"ReadVShiftX", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm : LMULReadAdvance<"ReadVICmpV", 0>;
+defm : LMULReadAdvance<"ReadVICmpX", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
+defm : LMULReadAdvance<"ReadVIMulV", 0>;
+defm : LMULReadAdvance<"ReadVIMulX", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm : LMULReadAdvance<"ReadVIMovV", 0>;
+defm : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// 13. Vector Floating-Point Instructions
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
+defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
+
+// 14. Vector Reduction Operations
+def : ReadAdvance<ReadVIRedV, 0>;
+def : ReadAdvance<ReadVIRedV0, 0>;
+def : ReadAdvance<ReadVIWRedV, 0>;
+def : ReadAdvance<ReadVIWRedV0, 0>;
+def : ReadAdvance<ReadVFRedV, 0>;
+def : ReadAdvance<ReadVFRedV0, 0>;
+def : ReadAdvance<ReadVFRedOV, 0>;
+def : ReadAdvance<ReadVFRedOV0, 0>;
+def : ReadAdvance<ReadVFWRedV, 0>;
+def : ReadAdvance<ReadVFWRedV0, 0>;
+def : ReadAdvance<ReadVFWRedOV, 0>;
+def : ReadAdvance<ReadVFWRedOV0, 0>;
+
+// 15. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
+
+// 16. Vector Permutation Instructions
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
+defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVMov1V, 0>;
+def : ReadAdvance<ReadVMov2V, 0>;
+def : ReadAdvance<ReadVMov4V, 0>;
+def : ReadAdvance<ReadVMov8V, 0>;
+
+// Others
+def : ReadAdvance<ReadVMask, 0>;
+def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
+foreach mx = SchedMxList in {
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;
+ foreach sew = SchedSEWSet<mx>.val in
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;
+}
+
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedQ;
-defm : UnsupportedSchedV;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s
index d1ab4b3b6a7e0..1a7812e70438d 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s
@@ -67,26 +67,34 @@ fcvt.s.w ft0, a0
# CHECK-NEXT: [5] - Andes45FMV
# CHECK-NEXT: [6] - Andes45LSU
# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - - 56.00 4.00 4.00 2.00 - -
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - - 56.00 4.00 4.00 2.00 - - - - - - - - - -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - fadd.s ft0, fa0, fa1
-# CHECK-NEXT: - - - 19.00 - - - - - fdiv.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - 1.00 - - - - fadd.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - 1.00 - - - - fmul.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - 1.00 - - - - fmadd.s ft0, fa0, fa1, fa2
-# CHECK-NEXT: - - - 19.00 - - - - - fdiv.s ft0, fa0, fa1
-# CHECK-NEXT: - - - 18.00 - - - - - fsqrt.s ft0, fa0
-# CHECK-NEXT: - - - - - - 1.00 - - fsgnj.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - - - 1.00 - - fmv.x.w a0, fa0
-# CHECK-NEXT: - - - - - 1.00 - - - fmin.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - - 1.00 - - - fclass.s a0, fa0
-# CHECK-NEXT: - - - - - 1.00 - - - feq.s a0, fa0, fa1
-# CHECK-NEXT: - - - - - 1.00 - - - fcvt.s.w ft0, a0
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fadd.s ft0, fa0, fa1
+# CHECK-NEXT: - - - 19.00 - - - - - - - - - - - - - fdiv.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fadd.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fmul.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fmadd.s ft0, fa0, fa1, fa2
+# CHECK-NEXT: - - - 19.00 - - - - - - - - - - - - - fdiv.s ft0, fa0, fa1
+# CHECK-NEXT: - - - 18.00 - - - - - - - - - - - - - fsqrt.s ft0, fa0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - fsgnj.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - fmv.x.w a0, fa0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - fmin.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - fclass.s a0, fa0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - feq.s a0, fa0, fa1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - fcvt.s.w ft0, a0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
index d90dce8c5c3fc..3227ecfa4a372 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
@@ -133,55 +133,63 @@ bext a0, a0, a0
# CHECK-NEXT: [5] - Andes45FMV
# CHECK-NEXT: [6] - Andes45LSU
# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: 10.00 11.00 1.00 - - - - 16.00 80.00
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: 10.00 11.00 1.00 - - - - 16.00 80.00 - - - - - - - -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - 1.00 - - - - - - - add a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - sub a1, a1, a1
-# CHECK-NEXT: - 1.00 - - - - - - - addw a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - subw a0, a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - slli a0, a0, 4
-# CHECK-NEXT: 1.00 - - - - - - - - slliw a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - srl a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - srlw a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 1.00 mul a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 1.00 mulw a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 39.00 div a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 39.00 divw a0, a0, a0
-# CHECK-NEXT: - - - - - - - 1.00 - lb a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - lh a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - lw a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - ld a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - flw fa0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - fld fa0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sb a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sh a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sw a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sd a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - amoswap.w a0, a1, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - amoswap.d a0, a1, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - lr.w a0, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - lr.d a0, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - sc.w a0, a1, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - sc.d a0, a1, (a0)
-# CHECK-NEXT: - - 1.00 - - - - - - csrrw a0, mstatus, zero
-# CHECK-NEXT: - 1.00 - - - - - - - sh1add a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - sh1add.uw a0, a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - rori a0, a0, 4
-# CHECK-NEXT: 1.00 - - - - - - - - roriw a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - rol a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - rolw a0, a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - clz a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - clzw a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - clmul a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - bclri a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - bclr a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - bexti a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - bext a0, a0, a0
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - sub a1, a1, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - slli a0, a0, 4
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - slliw a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - srl a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - srlw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - mulw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 39.00 - - - - - - - - div a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 39.00 - - - - - - - - divw a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lb a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lh a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lw a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ld a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - flw fa0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - fld fa0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sb a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sh a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sw a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sd a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - amoswap.w a0, a1, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - amoswap.d a0, a1, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lr.w a0, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lr.d a0, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sc.w a0, a1, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sc.d a0, a1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - csrrw a0, mstatus, zero
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - sh1add a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - rori a0, a0, 4
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - roriw a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - rol a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - rolw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - clz a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - clzw a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - clmul a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - bclri a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - bclr a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - bexti a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - bext a0, a0, a0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 012
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
new file mode 100644
index 0000000000000..dc4122ab19293
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
@@ -0,0 +1,6837 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Basic arithmetic operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vsub.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
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+vmadc.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadc.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmadc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmadc.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmadc.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmsbc.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsbc.vvm v8, v8, v8, v0
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+vmsbc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmsbc.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmsbc.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vrsub.vi v8, v8, 12
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+vrsub.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vrsub.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrsub.vx v8, v8, x30
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+vrsub.vx v8, v8, x30
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+vsetvli x28, x0, e16, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssub.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwaddu.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwaddu.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwadd.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwadd.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwsubu.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwsubu.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwsub.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwsub.wx v8, v16, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 1120.00 - - - - - - 1120.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s
new file mode 100644
index 0000000000000..3445098403df3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s
@@ -0,0 +1,4345 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Bitwise and logical operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnsrl.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wx v8, v16, x30
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+vsetvli x28, x0, e32, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssrl.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
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+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s
new file mode 100644
index 0000000000000..7aaa351bbbc3e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s
@@ -0,0 +1,2721 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Comparison operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmseq.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmseq.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vmseq.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmsle.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmsle.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmsle.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmsle.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vmsle.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vmsle.vi v8, v8, 12
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+vsetvli x28, x0, e8, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmsgt.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmsltu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmsltu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmslt.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmslt.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 440.00 - - - - - - 440.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s
new file mode 100644
index 0000000000000..f7273e5851d81
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s
@@ -0,0 +1,1774 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Conversion operations
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf2 v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf2 v8, v16
+
+vsetvli x28, x0, e32, mf2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf4 v8, v16
+
+vsetvli x28, x0, e32, mf2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf4 v8, v16
+
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf8 v8, v16
+
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf8 v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.f.x.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.x.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.xu.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.x.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.x.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.xu.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.x.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.xu.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.x.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.xu.f.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 281.00 - - - - - - 56.00 - - 225.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.x.v v8, v8
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+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s
new file mode 100644
index 0000000000000..7f5df0694a4c5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s
@@ -0,0 +1,2202 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Fused multiply-add operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmacc.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmacc.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadd.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadd.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsac.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsac.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsub.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmacc.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmacc.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmsac.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmsac.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmacc.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmsac.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmsac.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 353.00 - - - - - - - - - - - 353.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s
new file mode 100644
index 0000000000000..7cfa80d5033af
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s
@@ -0,0 +1,5616 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Floating point operations
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfeq.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfge.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfge.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfgt.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfgt.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfle.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfle.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmflt.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmflt.vv v8, v8, v8
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+vsetvli x28, x0, e32, m8, tu, mu
+vfsgnj.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfsgnj.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfsgnj.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfsgnj.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfsgnj.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vfsgnjx.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vfsgnjx.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfsgnjx.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfsgnjx.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.wf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.wv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmul.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmul.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.wf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.wv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFDIV VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWSUB_WV vfwsub.wv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 915.00 - - - - - - - - 90.00 360.00 - 435.00 - 30.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwsub.wv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s
new file mode 100644
index 0000000000000..6d4a85daadaf5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s
@@ -0,0 +1,1881 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Mask operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmand.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmnand.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmandn.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmxor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmnor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmorn.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmxnor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsbf.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsif.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsof.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m8, tu, mu
+vid.v v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vcpop.m x8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfirst.m x8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VFIRST_M vfirst.m s0, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 301.00 - - - - - - - - - - - - 301.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s
new file mode 100644
index 0000000000000..e9fa22065fd37
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s
@@ -0,0 +1,1125 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Min/max operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmax.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmax.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmaxu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmaxu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmin.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmin.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vminu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vminu.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 176.00 - - - - - - 176.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s
new file mode 100644
index 0000000000000..0405f8463299f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s
@@ -0,0 +1,3001 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Multiplication and division operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmul.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmul.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vdiv.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vdiv.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vdivu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vdivu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
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+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmulhsu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmul.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmul.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulu.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsmul.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vsmul.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 486.00 - - - - - - - 176.00 - - - 310.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s
new file mode 100644
index 0000000000000..40ca2678c30cc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s
@@ -0,0 +1,3521 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Permutation and shuffle operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.x v8, x8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.i v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.x.s x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.s.x v8, x8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv1r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv2r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv4r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv8r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+viota.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m8, tu, mu
+vcompress.vm v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslide1up.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslide1down.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslideup.vx v8, v16, x30
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+vrgather.vv v8, v16, v24
+
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
+
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+vsetvli x28, x0, e64, m8, tu, mu
+vrgather.vi v8, v16, 12
+
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+
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+
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+vsetvli x28, x0, e32, m1, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vmerge.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMASK VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 572.00 - - - - - - 132.00 - - 15.00 - - 22.00 403.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vmv.x.s s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vmv.x.s s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
new file mode 100644
index 0000000000000..1cbf9176b31aa
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
@@ -0,0 +1,1841 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Reduction operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredand.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmax.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredminu.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmin.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredor.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredsum.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredxor.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vwredsum.vs v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredmax.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredmin.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredosum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredusum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfwredosum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfwredusum.vs v8, v8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 294.00 - - - - - - 212.00 - - 30.00 - 52.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vredand.vs v8, v8, v8
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwredusum.vs v8, v8, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s
new file mode 100644
index 0000000000000..375c615c0cc61
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s
@@ -0,0 +1,557 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vse8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vse16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vse32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vse64.v v8, (a0)
+
+# Unit-stride mask load/store
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vlm.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vsm.v v8, (a0)
+
+# Fault-only-first
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8ff.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16ff.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32ff.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLE64FF_V vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 80.00 - - - - - - - - - - 80.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s
new file mode 100644
index 0000000000000..8e59cba148c82
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s
@@ -0,0 +1,331 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v v8, (a0), t0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSE64_V vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 44.00 - - - - - - - - - - 44.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s
new file mode 100644
index 0000000000000..096d4918df03a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s
@@ -0,0 +1,4742 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg6e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg7e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg8e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vsseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg6e8.v v8,(a0)
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+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E64_V vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E64_V vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E64_V vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E64_V vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG5E64_V vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG6E64_V vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG7E64_V vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSEG8E64_V vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG5E64_V vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG6E64_V vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG7E64_V vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSSEG8E64_V vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG5E64_V vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG6E64_V vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG7E64_V vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSSSEG8E64_V vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG5E64FF_V vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG6E64FF_V vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG7E64FF_V vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLSEG8E64FF_V vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG5EI64_V vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG6EI64_V vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG7EI64_V vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXSEG8EI64_V vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG5EI64_V vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG6EI64_V vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG7EI64_V vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXSEG8EI64_V vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG5EI64_V vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG6EI64_V vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG7EI64_V vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXSEG8EI64_V vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG5EI64_V vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG6EI64_V vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG7EI64_V vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXSEG8EI64_V vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 770.00 - - - - - - - - - - 770.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg7ei8.v v8, (a0), v16
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+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s
new file mode 100644
index 0000000000000..af659fcffa476
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s
@@ -0,0 +1,603 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vluxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vluxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vluxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vluxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vloxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vloxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vloxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vloxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsuxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsuxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsuxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsuxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsoxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsoxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsoxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU VSOXEI64_V vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 88.00 - - - - - - - - - - 88.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
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