[llvm] 20cc9fe - [RISCV] Remove now unused ixlenimm Operand. NFC (#171896)

via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 11 14:46:51 PST 2025


Author: Craig Topper
Date: 2025-12-11T14:46:47-08:00
New Revision: 20cc9fe95d53747f96bc8d56b8a5ca611fd7f157

URL: https://github.com/llvm/llvm-project/commit/20cc9fe95d53747f96bc8d56b8a5ca611fd7f157
DIFF: https://github.com/llvm/llvm-project/commit/20cc9fe95d53747f96bc8d56b8a5ca611fd7f157.diff

LOG: [RISCV] Remove now unused ixlenimm Operand. NFC (#171896)

Going forward I think we should add Operands with specific OperandType
so we no longer need a generic immediate Operand.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9a4eb12ca0eb0..708414496f4b6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -489,9 +489,6 @@ def csr_sysreg : RISCVOp, TImmLeaf<XLenVT, "return isUInt<12>(Imm);"> {
   let OperandType = "OPERAND_UIMM12";
 }
 
-// A parameterized register class alternative to i32imm/i64imm from Target.td.
-def ixlenimm : Operand<XLenVT>;
-
 // Condition code used by select and short forward branch pseudos.
 def cond_code : RISCVOp {
   let OperandType = "OPERAND_COND_CODE";


        


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