[llvm] [SPIRV] Restrict OpName generation to major values (PR #171886)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 11 11:13:35 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-spir-v
@llvm/pr-subscribers-llvm-globalisel
Author: Steven Perron (s-perron)
<details>
<summary>Changes</summary>
Refines OpName emission to only target Global Variables, Functions,
Function Parameters, Local Variables (allocas/phis), and Basic Blocks.
This reduces binary size and clutter by avoiding OpName for every
intermediate instruction (arithmetic, casts, etc.), while preserving
readability for interfaces and program structure.
Also updates the test suite to align with this change:
- Removes OpName checks for intermediate instructions.
- Adds side-effects (e.g., volatile stores) to tests where instructions
were previously kept alive solely by their OpName usage.
- Updates checks to use generic ID matching where specific names are no
longer available.
- Adds debug-info/opname-filtering.ll to verify the new policy.
---
Patch is 103.17 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171886.diff
40 Files Affected:
- (modified) llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp (+14)
- (modified) llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll (+2-1)
- (modified) llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll (+1)
- (modified) llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll (+2-1)
- (modified) llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll (+1)
- (modified) llvm/test/CodeGen/SPIRV/TruncToBool.ll (+2-1)
- (added) llvm/test/CodeGen/SPIRV/debug-info/opname-filtering.ll (+46)
- (modified) llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll (+1-1)
- (modified) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll (+4-7)
- (modified) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll (+8-5)
- (modified) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll (+88-120)
- (modified) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll (+2-1)
- (modified) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll (+18-1)
- (modified) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/replacements.ll (+9-17)
- (modified) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll (+6-13)
- (modified) llvm/test/CodeGen/SPIRV/freeze.ll (+5-13)
- (modified) llvm/test/CodeGen/SPIRV/instructions/bitwise-i1.ll (+16-4)
- (modified) llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll (+30-14)
- (modified) llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll (+1-3)
- (modified) llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll (+9-15)
- (modified) llvm/test/CodeGen/SPIRV/opencl/vload2.ll (+11-12)
- (modified) llvm/test/CodeGen/SPIRV/optimizations/add-check-overflow.ll (+4-9)
- (modified) llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll (+4-6)
- (modified) llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll (+4-10)
- (modified) llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll (+1-2)
- (modified) llvm/test/CodeGen/SPIRV/select-builtin.ll (+2-1)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/OpDot.ll (+6-2)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll (+1-2)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll (+1-4)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/fadd.ll (+39-38)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll (+90-180)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/fdiv.ll (+16-16)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/fmul.ll (+16-16)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/fneg.ll (+15-15)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/fp_contract_reassoc_fast_mode.ll (+2-4)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/frem.ll (+16-16)
- (modified) llvm/test/CodeGen/SPIRV/transcoding/fsub.ll (+17-16)
- (modified) llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll (+6-10)
- (modified) llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll (+28-48)
- (modified) llvm/test/CodeGen/SPIRV/zero-length-array.ll (-3)
``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index 4f754021f5544..bfbc72802a86c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -361,6 +361,20 @@ static void emitAssignName(Instruction *I, IRBuilder<> &B) {
expectIgnoredInIRTranslation(I))
return;
+ // We want to be conservative when adding the names because they can interfere
+ // with later optimizations.
+ bool KeepName = false;
+ if (isa<AllocaInst>(I)) {
+ KeepName = true;
+ } else if (auto *CI = dyn_cast<CallBase>(I)) {
+ Function *F = CI->getCalledFunction();
+ if (F && F->getName().starts_with("llvm.spv.alloca"))
+ KeepName = true;
+ }
+
+ if (!KeepName)
+ return;
+
if (isa<CallBase>(I)) {
// TODO: this is a temporary workaround meant to prevent inserting internal
// noise into the generated binary; remove once we rework the entire
diff --git a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
index 86581a5468405..79ca18bb70a20 100644
--- a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
+++ b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
@@ -5,9 +5,10 @@
;; LLVM IR was generated with -cl-std=c++ option
-define spir_kernel void @test(float %op1, float %op2) {
+define spir_kernel void @test(float %op1, float %op2, i32 addrspace(1)* %out) {
entry:
%call = call spir_func i32 @_Z14isgreaterequalff(float %op1, float %op2)
+ store i32 %call, i32 addrspace(1)* %out
ret void
}
diff --git a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
index 58638578bb3f0..0c6f6c9a53b1d 100644
--- a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
+++ b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
@@ -4,5 +4,6 @@ target triple = "spirv64"
define void @addrspacecast(ptr addrspace(9) %a) {
; CHECK: unable to legalize instruction: %{{.*}}:pid(p4) = G_ADDRSPACE_CAST %{{.*}}:pid(p9)
%res1 = addrspacecast ptr addrspace(9) %a to ptr addrspace(4)
+ store i8 0, ptr addrspace(4) %res1
ret void
}
diff --git a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll
index 229f2234220ab..e7a9decf0c327 100644
--- a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll
+++ b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll
@@ -1,8 +1,9 @@
; RUN: not llc --global-isel %s -filetype=null 2>&1 | FileCheck %s
target triple = "spirv64"
-define void @do_load(ptr addrspace(9) %a) {
+define void @do_load(ptr addrspace(9) %a, ptr addrspace(1) %out) {
; CHECK: unable to legalize instruction: %{{.*}}:iid(s32) = G_LOAD %{{.*}}:pid(p9)
%val = load i32, ptr addrspace(9) %a
+ store i32 %val, ptr addrspace(1) %out
ret void
}
diff --git a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
index 6e414f79bdde5..125cc6137e78b 100644
--- a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
+++ b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
@@ -24,6 +24,7 @@ entry:
%selected = select i1 %3, i8 0, i8 1
%frombool.i = zext i1 %3 to i8
%sum = add i8 %frombool.i, %selected
+ store volatile i8 %sum, i8 addrspace(4)* %ptridx.ascast.i.i, align 1
store i8 %selected, i8 addrspace(4)* %ptridx.ascast.i.i, align 1
ret void
}
diff --git a/llvm/test/CodeGen/SPIRV/TruncToBool.ll b/llvm/test/CodeGen/SPIRV/TruncToBool.ll
index 6682c23f34e96..8e23f4eb06914 100644
--- a/llvm/test/CodeGen/SPIRV/TruncToBool.ll
+++ b/llvm/test/CodeGen/SPIRV/TruncToBool.ll
@@ -3,10 +3,11 @@
; CHECK-SPIRV: OpBitwiseAnd
; CHECK-SPIRV-NEXT: OpINotEqual
-define spir_kernel void @test(i32 %op1, i32 %op2, i8 %op3) {
+define spir_kernel void @test(i32 %op1, i32 %op2, i8 %op3, i32 addrspace(1)* %out) {
entry:
%0 = trunc i8 %op3 to i1
%call = call spir_func i32 @_Z14__spirv_Selectbii(i1 zeroext %0, i32 %op1, i32 %op2)
+ store i32 %call, i32 addrspace(1)* %out
ret void
}
diff --git a/llvm/test/CodeGen/SPIRV/debug-info/opname-filtering.ll b/llvm/test/CodeGen/SPIRV/debug-info/opname-filtering.ll
new file mode 100644
index 0000000000000..022dc28fedc6a
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/debug-info/opname-filtering.ll
@@ -0,0 +1,46 @@
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; Verify that OpName is generated for Global Variables, Functions, Parameters,
+; Local Variables (Alloca), and Basic Blocks (Labels).
+; We preserve these names because they significantly improve the readability of
+; the generated SPIR-V binary and are unlikely to inhibit optimizations (like
+; Dead Code Elimination) since they define the interface or storage of the program.
+
+; 1. Global variables ("GlobalVar")
+; CHECK-DAG: OpName %[[#GlobalVar:]] "GlobalVar"
+
+; 2. Functions ("test_names")
+; CHECK-DAG: OpName %[[#Func:]] "test_names"
+
+; 3. Function parameters ("param")
+; CHECK-DAG: OpName %[[#Param:]] "param"
+
+; 4. Local variables (AllocaInst) ("localVar")
+; CHECK-DAG: OpName %[[#LocalVar:]] "localVar"
+
+; 5. Basic Blocks ("entry", "body")
+; CHECK-DAG: OpName %[[#Entry:]] "entry"
+; CHECK-DAG: OpName %[[#Body:]] "body"
+
+; Verify that OpName is NOT generated for intermediate instructions
+; (arithmetic, etc.). This reduces file size and noise, and prevents
+; potential interference with optimizations where the presence of a Name
+; (user) might incorrectly keep a dead instruction alive in some test scenarios.
+
+; CHECK-NOT: OpName %{{.*}} "add"
+; CHECK-NOT: OpName %{{.*}} "sub"
+
+ at GlobalVar = global i32 0
+
+define spir_func void @test_names(i32 %param) {
+entry:
+ %localVar = alloca i32
+ br label %body
+
+body:
+ %add = add i32 %param, 1
+ %sub = sub i32 %add, 1
+ store i32 %sub, i32* %localVar
+ ret void
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll b/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll
index f1e092732558e..019e60dad41ae 100644
--- a/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll
+++ b/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK: OpEntryPoint Kernel %[[#Func:]] "test" %[[#Interface1:]] %[[#Interface2:]] %[[#Interface3:]] %[[#Interface4:]]
+; CHECK: OpEntryPoint Kernel %[[#Func:]] "test" %[[#Interface3:]] %[[#Interface4:]] %[[#Interface1:]] %[[#Interface2:]]
; CHECK-DAG: OpName %[[#Func]] "test"
; CHECK-DAG: OpName %[[#Interface1]] "var"
; CHECK-DAG: OpName %[[#Interface3]] "var2"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
index 4428a2049f9ce..0b39ee853b057 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
@@ -1,17 +1,14 @@
; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_cache_controls
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - -filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - -filetype=obj | spirv-val %}
; CHECK-SPIRV: Capability CacheControlsINTEL
; CHECK-SPIRV: Extension "SPV_INTEL_cache_controls"
-; CHECK-SPIRV-DAG: OpName %[[#Ptr1:]] "ptr1"
-; CHECK-SPIRV-DAG: OpName %[[#Ptr2:]] "ptr2"
-; CHECK-SPIRV-DAG: OpName %[[#Ptr3:]] "ptr3"
-; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr1]] CacheControlLoadINTEL 0 1
-; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr2]] CacheControlLoadINTEL 1 1
-; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr3]] CacheControlStoreINTEL 2 3
+; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr1:]] CacheControlLoadINTEL 0 1
+; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr2:]] CacheControlLoadINTEL 1 1
+; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr3:]] CacheControlStoreINTEL 2 3
; CHECK-SPIRV: OpExtInst %[[#]] %[[#]] prefetch %[[#Ptr1]] %[[#]]
; CHECK-SPIRV: OpExtInst %[[#]] %[[#]] prefetch %[[#Ptr2]] %[[#]]
; CHECK-SPIRV: OpExtInst %[[#]] %[[#]] prefetch %[[#Ptr3]] %[[#]]
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll
index 635015c970d3e..34c3741cfc6ef 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll
@@ -9,22 +9,25 @@
; CHECK: OpExtension "SPV_INTEL_fp_max_error"
; CHECK: OpName %[[#CalleeName:]] "callee"
-; CHECK: OpName %[[#F3:]] "f3"
-; CHECK: OpDecorate %[[#F3]] FPMaxErrorDecorationINTEL 1075838976
+; CHECK: OpDecorate %[[#F3:]] FPMaxErrorDecorationINTEL 1075838976
; CHECK: OpDecorate %[[#Callee:]] FPMaxErrorDecorationINTEL 1065353216
; CHECK: %[[#FloatTy:]] = OpTypeFloat 32
-; CHECK: %[[#Callee]] = OpFunctionCall %[[#FloatTy]] %[[#CalleeName]]
define float @callee(float %f1, float %f2) {
entry:
ret float %f1
}
-define void @test_fp_max_error_decoration(float %f1, float %f2) {
+; CHECK: %[[#F3]] = OpFDiv %[[#FloatTy]]
+; CHECK: %[[#Callee]] = OpFunctionCall %[[#FloatTy]] %[[#CalleeName]]
+
+define void @test_fp_max_error_decoration(float %f1, float %f2, float* %out) {
entry:
%f3 = fdiv float %f1, %f2, !fpmath !0
-call float @callee(float %f1, float %f2), !fpmath !1
+store volatile float %f3, float* %out
+%call = call float @callee(float %f1, float %f2), !fpmath !1
+store volatile float %call, float* %out
ret void
}
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
index 81497f26f1aef..c7326cd7b4cfa 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
@@ -4,80 +4,34 @@
; CHECK-DAG: Capability FloatControls2
; CHECK: Extension "SPV_KHR_float_controls2"
-; CHECK: OpName %[[#addRes:]] "addRes"
-; CHECK: OpName %[[#subRes:]] "subRes"
-; CHECK: OpName %[[#mulRes:]] "mulRes"
-; CHECK: OpName %[[#divRes:]] "divRes"
-; CHECK: OpName %[[#remRes:]] "remRes"
-; CHECK: OpName %[[#negRes:]] "negRes"
-; CHECK: OpName %[[#oeqRes:]] "oeqRes"
-; CHECK: OpName %[[#oneRes:]] "oneRes"
-; CHECK: OpName %[[#oltRes:]] "oltRes"
-; CHECK: OpName %[[#ogtRes:]] "ogtRes"
-; CHECK: OpName %[[#oleRes:]] "oleRes"
-; CHECK: OpName %[[#ogeRes:]] "ogeRes"
-; CHECK: OpName %[[#ordRes:]] "ordRes"
-; CHECK: OpName %[[#ueqRes:]] "ueqRes"
-; CHECK: OpName %[[#uneRes:]] "uneRes"
-; CHECK: OpName %[[#ultRes:]] "ultRes"
-; CHECK: OpName %[[#ugtRes:]] "ugtRes"
-; CHECK: OpName %[[#uleRes:]] "uleRes"
-; CHECK: OpName %[[#ugeRes:]] "ugeRes"
-; CHECK: OpName %[[#unoRes:]] "unoRes"
-; CHECK: OpName %[[#modRes:]] "modRes"
-; CHECK: OpName %[[#maxRes:]] "maxRes"
-; CHECK: OpName %[[#maxCommonRes:]] "maxCommonRes"
-; CHECK: OpName %[[#addResV:]] "addResV"
-; CHECK: OpName %[[#subResV:]] "subResV"
-; CHECK: OpName %[[#mulResV:]] "mulResV"
-; CHECK: OpName %[[#divResV:]] "divResV"
-; CHECK: OpName %[[#remResV:]] "remResV"
-; CHECK: OpName %[[#negResV:]] "negResV"
-; CHECK: OpName %[[#oeqResV:]] "oeqResV"
-; CHECK: OpName %[[#oneResV:]] "oneResV"
-; CHECK: OpName %[[#oltResV:]] "oltResV"
-; CHECK: OpName %[[#ogtResV:]] "ogtResV"
-; CHECK: OpName %[[#oleResV:]] "oleResV"
-; CHECK: OpName %[[#ogeResV:]] "ogeResV"
-; CHECK: OpName %[[#ordResV:]] "ordResV"
-; CHECK: OpName %[[#ueqResV:]] "ueqResV"
-; CHECK: OpName %[[#uneResV:]] "uneResV"
-; CHECK: OpName %[[#ultResV:]] "ultResV"
-; CHECK: OpName %[[#ugtResV:]] "ugtResV"
-; CHECK: OpName %[[#uleResV:]] "uleResV"
-; CHECK: OpName %[[#ugeResV:]] "ugeResV"
-; CHECK: OpName %[[#unoResV:]] "unoResV"
-; CHECK: OpName %[[#modResV:]] "modResV"
-; CHECK: OpName %[[#maxResV:]] "maxResV"
-; CHECK: OpName %[[#maxCommonResV:]] "maxCommonResV"
-; CHECK: OpDecorate %[[#subRes]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#mulRes]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#divRes]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#remRes]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#negRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#oeqRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#oltRes]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#ogtRes]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#oleRes]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#ogeRes]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#ordRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#ueqRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#maxRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#maxCommonRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#subResV]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#mulResV]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#divResV]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#remResV]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#negResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#oeqResV]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#oltResV]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#ogtResV]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#oleResV]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#ogeResV]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#ordResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#ueqResV]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#maxResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#maxCommonResV]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#subRes:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#mulRes:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#divRes:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#remRes:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#negRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#oeqRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#oltRes:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#ogtRes:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#oleRes:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#ogeRes:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#ordRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#ueqRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#maxRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#maxCommonRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#subResV:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#mulResV:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#divResV:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#remResV:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#negResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#oeqResV:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#oltResV:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#ogtResV:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#oleResV:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#ogeResV:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#ordResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#ueqResV:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#maxResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#maxCommonResV:]] FPFastMathMode NotNaN|NotInf
@G_addRes = global float 0.0
@G_subRes = global float 0.0
@@ -139,101 +93,115 @@ declare dso_local spir_func noundef nofpclass(nan inf) <2 x float> @_Z23__spirv_
define weak_odr dso_local spir_kernel void @foo(float %1, float %2) {
entry:
%addRes = fadd float %1, %2
- store float %addRes, float* @G_addRes
+ store volatile float %addRes, float* @G_addRes
+ ; CHECK: %[[#subRes]] = OpFSub
%subRes = fsub nnan float %1, %2
- store float %subRes, float* @G_subRes
+ store volatile float %subRes, float* @G_subRes
+ ; CHECK: %[[#mulRes]] = OpFMul
%mulRes = fmul ninf float %1, %2
- store float %mulRes, float* @G_mulRes
+ store volatile float %mulRes, float* @G_mulRes
+ ; CHECK: %[[#divRes]] = OpFDiv
%divRes = fdiv nsz float %1, %2
- store float %divRes, float* @G_divRes
+ store volatile float %divRes, float* @G_divRes
+ ; CHECK: %[[#remRes]] = OpFRem
%remRes = frem arcp float %1, %2
- store float %remRes, float* @G_remRes
+ store volatile float %remRes, float* @G_remRes
+ ; CHECK: %[[#negRes]] = OpFNegate
%negRes = fneg fast float %1
- store float %negRes, float* @G_negRes
+ store volatile float %negRes, float* @G_negRes
+ ; CHECK: %[[#oeqRes]] = OpFOrdEqual
%oeqRes = fcmp nnan ninf oeq float %1, %2
- store i1 %oeqRes, i1* @G_oeqRes
+ store volatile i1 %oeqRes, i1* @G_oeqRes
%oneRes = fcmp one float %1, %2, !spirv.Decorations !3
- store i1 %oneRes, i1* @G_oneRes
+ store volatile i1 %oneRes, i1* @G_oneRes
+ ; CHECK: %[[#oltRes]] = OpFOrdLessThan
%oltRes = fcmp nnan olt float %1, %2, !spirv.Decorations !3
- store i1 %oltRes, i1* @G_oltRes
+ store volatile i1 %oltRes, i1* @G_oltRes
+ ; CHECK: %[[#ogtRes]] = OpFOrdGreaterThan
%ogtRes = fcmp ninf ogt float %1, %2, !spirv.Decorations !3
- store i1 %ogtRes, i1* @G_ogtRes
+ store volatile i1 %ogtRes, i1* @G_ogtRes
+ ; CHECK: %[[#oleRes]] = OpFOrdLessThanEqual
%oleRes = fcmp nsz ole float %1, %2, !spirv.Decorations !3
- store i1 %oleRes, i1* @G_oleRes
+ store volatile i1 %oleRes, i1* @G_oleRes
+ ; CHECK: %[[#ogeRes]] = OpFOrdGreaterThanEqual
%ogeRes = fcmp arcp oge float %1, %2, !spirv.Decorations !3
- store i1 %ogeRes, i1* @G_ogeRes
+ store volatile i1 %ogeRes, i1* @G_ogeRes
+ ; CHECK: %[[#ordRes]] = OpOrdered
%ordRes = fcmp fast ord float %1, %2, !spirv.Decorations !3
- store i1 %ordRes, i1* @G_ordRes
+ store volatile i1 %ordRes, i1* @G_ordRes
+ ; CHECK: %[[#ueqRes]] = OpFUnordEqual
%ueqRes = fcmp nnan ninf ueq float %1, %2, !spirv.Decorations !3
- store i1 %ueqRes, i1* @G_ueqRes
+ store volatile i1 %ueqRes, i1* @G_ueqRes
%uneRes = fcmp une float %1, %2, !spirv.Decorations !3
- store i1 %uneRes, i1* @G_uneRes
+ store volatile i1 %uneRes, i1* @G_uneRes
%ultRes = fcmp ult float %1, %2, !spirv.Decorations !3
- store i1 %ultRes, i1* @G_ultRes
+ store volatile i1 %ultRes, i1* @G_ultRes
%ugtRes = fcmp ugt float %1, %2, !spirv.Decorations !3
- store i1 %ugtRes, i1* @G_ugtRes
+ store volatile i1 %ugtRes, i1* @G_ugtRes
%uleRes = fcmp ule float %1, %2, !spirv.Decorations !3
- store i1 %uleRes, i1* @G_uleRes
+ store volatile i1 %uleRes, i1* @G_uleRes
%ugeRes = fcmp uge float %1, %2, !spirv.Decorations !3
- store i1 %ugeRes, i1* @G_ugeRes
+ store volatile i1 %ugeRes, i1* @G_ugeRes
%unoRes = fcmp uno float %1, %2, !spirv.Decorations !3
- store i1 %unoRes, i1* @G_unoRes
+ store volatile i1 %unoRes, i1* @G_unoRes
%modRes = call spir_func float @_Z4fmodff(float %1, float %2)
- store float %modRes, float* @G_modRes
+ store volatile float %modRes, float* @G_modRes
+ ; CHECK: %[[#maxRes]] = OpExtInst %[[#]] %[[#]] fmax
%maxRes = tail call fas...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/171886
More information about the llvm-commits
mailing list