[llvm] [AMDGPU][True16] extractEltcheap check 16bit in true16 mode (PR #171762)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 11 11:13:11 PST 2025
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/171762
>From b5d8025c239469649174adade7f355e7a4547c4f Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Wed, 10 Dec 2025 22:07:45 -0500
Subject: [PATCH] use 16bit for extractElt cost check
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 +--
.../build-vector-packed-partial-undef.ll | 37 ++++++++++++++-----
.../CodeGen/AMDGPU/extract-subvector-16bit.ll | 28 +++++++-------
3 files changed, 44 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 4651d7d9d3adf..025f740ad4d78 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2232,10 +2232,9 @@ bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
}
bool SITargetLowering::isExtractVecEltCheap(EVT VT, unsigned Index) const {
- // TODO: This should be more aggressive, particular for 16-bit element
- // vectors. However there are some mixed improvements and regressions.
EVT EltTy = VT.getVectorElementType();
- return EltTy.getSizeInBits() % 32 == 0;
+ unsigned MinAlign = Subtarget->useRealTrue16Insts() ? 16 : 32;
+ return EltTy.getSizeInBits() % MinAlign == 0;
}
bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
index f7dbcd137e742..9db34d0f1ed1b 100644
--- a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
@@ -586,14 +586,33 @@ define void @undef_hi_op_v2f16(half %arg0) {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: undef_hi_op_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
-; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use v0
-; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: undef_hi_op_v2f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT: ;;#ASMSTART
+; GFX11-FAKE16-NEXT: ; use v0
+; GFX11-FAKE16-NEXT: ;;#ASMEND
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-SDAG-LABEL: undef_hi_op_v2f16:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.h, 0x7e00
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-SDAG-NEXT: ; use v0
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
+; GFX11-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-GISEL-LABEL: undef_hi_op_v2f16:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-GISEL-NEXT: ; use v0
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMEND
+; GFX11-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
%undef.hi = insertelement <2 x half> poison, half %arg0, i32 0
%op = fadd <2 x half> %undef.hi, <half 1.0, half 1.0>
call void asm sideeffect "; use $0", "v"(<2 x half> %op);
@@ -663,7 +682,7 @@ define void @undef_hi_op_v2i16(i16 %arg0) {
; GFX11-TRUE16-SDAG-LABEL: undef_hi_op_v2i16:
; GFX11-TRUE16-SDAG: ; %bb.0:
; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-SDAG-NEXT: v_pk_add_u16 v0, 0x63, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-SDAG-NEXT: v_add_nc_u16 v0.l, 0x63, v0.l
; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
; GFX11-TRUE16-SDAG-NEXT: ; use v0
; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
index d370ea86e3dc8..6d3ea5f492373 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
@@ -132,14 +132,14 @@ define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1)
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB0_3: ; %exit
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 15, v3.l
+; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v2, 15, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB0_4:
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
@@ -762,14 +762,14 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB3_3: ; %exit
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 15, v3.l
+; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v2, 15, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB3_4:
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
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