[llvm] [ISel] Introduce llvm.clmul intrinsic (PR #168731)

[Craig Topper via llvm-commits]

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@@ -204,6 +204,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::ADD:
   case ISD::SUB:
   case ISD::MUL:
+  case ISD::CLMULR:
+  case ISD::CLMULH:
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topperc wrote:

This promotion is incorrect. We can't just create a larger node of the same opcode. For MULH, if the original type was i4, we need to do (SRL (CLMUL (AND X, 15), (AND Y, 15)), 4).

https://github.com/llvm/llvm-project/pull/168731