[llvm] [SDAG] Shrink (abds (sext x) (sext y)) (PR #171865)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: None (natanelh-mobileye)

<details>
<summary>Changes</summary>

sadly alive2 times out on this test... but if you have better luck,

https://alive2.llvm.org/ce/z/GBbJ-F

https://github.com/llvm/llvm-project/issues/171640

---
Full diff: https://github.com/llvm/llvm-project/pull/171865.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+15-1) 
- (modified) llvm/test/CodeGen/AArch64/arm64-vabs.ll (+33) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index bcdc37f1b81ea..56c5e907c3df8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5760,7 +5760,7 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
   if (N0 == N1)
     return DAG.getConstant(0, DL, VT);
 
-  SDValue X;
+  SDValue X, Y;
 
   // fold (abds x, 0) -> abs x
   if (sd_match(N, m_c_BinOp(ISD::ABDS, m_Value(X), m_Zero())) &&
@@ -5776,6 +5776,20 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
       DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
     return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
 
+  // fold (abds (sext x), (sext y)) -> (zext (abds x, y))
+  if (sd_match(N,
+               m_c_BinOp(ISD::ABDS, m_SExt(m_Value(X)), m_SExt(m_Value(Y)))) &&
+      X.getValueType() == Y.getValueType()) {
+    EVT SmallVT = X.getScalarValueSizeInBits() > Y.getScalarValueSizeInBits()
+                      ? X.getValueType()
+                      : Y.getValueType();
+    if (!LegalOperations || hasOperation(ISD::ABDS, SmallVT)) {
+      SDValue SmallABD = DAG.getNode(N->getOpcode(), DL, SmallVT, {X, Y});
+      SDValue ZExted = DAG.getZExtOrTrunc(SmallABD, DL, VT);
+      return ZExted;
+    }
+  }
+
   return SDValue();
 }
 
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index a3f4722e14406..15e55cd852feb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1,6 +1,39 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s -check-prefixes=CHECK,CHECK-SD
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+define <16 x i16> @sabd16b_i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: sabd16b_i16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    sabd.16b v0, v0, v1
+; CHECK-SD-NEXT:    ushll2.8h v1, v0, #0
+; CHECK-SD-NEXT:    ushll.8h v0, v0, #0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sabd16b_i16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sshll.8h v2, v0, #0
+; CHECK-GI-NEXT:    sshll.8h v3, v1, #0
+; CHECK-GI-NEXT:    sshll2.8h v4, v0, #0
+; CHECK-GI-NEXT:    sshll2.8h v5, v1, #0
+; CHECK-GI-NEXT:    ssubl.8h v6, v0, v1
+; CHECK-GI-NEXT:    ssubl2.8h v7, v0, v1
+; CHECK-GI-NEXT:    cmgt.8h v2, v3, v2
+; CHECK-GI-NEXT:    cmgt.8h v3, v5, v4
+; CHECK-GI-NEXT:    ssubl.8h v4, v1, v0
+; CHECK-GI-NEXT:    ssubl2.8h v1, v1, v0
+; CHECK-GI-NEXT:    mov.16b v0, v2
+; CHECK-GI-NEXT:    bif.16b v1, v7, v3
+; CHECK-GI-NEXT:    bsl.16b v0, v4, v6
+; CHECK-GI-NEXT:    ret
+  %aext = sext <16 x i8> %a to <16 x i16>
+  %bext = sext <16 x i8> %b to <16 x i16>
+  %abdiff = sub nsw <16 x i16> %aext, %bext
+  %abcmp = icmp slt <16 x i16> %aext, %bext
+  %ababs = sub nsw <16 x i16> %bext, %aext
+  %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
+  %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
+  ret <16 x i16> %absel
+}
 
 define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: sabdl8h:

``````````

</details>


https://github.com/llvm/llvm-project/pull/171865